1192
A-Si Planarization By Inductively Coupled Plasma Etch with Advanced Process Control

Monday, 14 May 2018
Ballroom 6ABC (Washington State Convention Center)

ABSTRACT WITHDRAWN

Since fin field effect transistors (FinFET) has been widely adopted in 16/14nm technology node and beyond, the process control becomes more and more critical. [1] A-Si thickness as well as uniformity control is rather rigorous.

In previous report, we have demonstrated the planarization of a-Si by inductively coupled plasma (ICP) with a fixed time [2]. Indeed, due to the process variation, the wafer level control of CMP cannot be too precise without specific process control. The temperature-only controlled etch amount to target thickness is limited and process window is restricted. Thus, one more etch factor need to be introduced for wider process window and more accurate control.

In this paper, a dynamic process time name as “trimming” function is simulated based on the incoming thickness and ‘trmming’ rate for better control the thickness after etching process. Trimming, namely time dependent etching, is more effective to the incoming thickness variation. In this planarization process, the process control focuses on two performances: the uniformity and the mean value. The uniformity is mainly control the “Hydra” parts, wlhich is equipped in the commercial ICP tools and can supply more than 100 temperature control units, while the mean value is mainly controlled by etching time. Our experimental results shows the temperature dependency of thickness control is -26.3Å/℃, while the trimming rate is -1.35 Å/s. Based on the experimental data, the time–dependent etching based on the input thickness is realized.

This work was partially sponsored by Shanghai Rising-Star Program(B type). The authors would like to thank Mr. Jiangang Liu, and Tongxun Guo from Lam research for the support of constructive discussion.

Reference:

[1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012.

[2] Y. Wang et al., “Poly-Si Planarization by ICP Plasma Etch at FinFET Technology”, ECS Trans. 77(3), 71-76, 2017.