Keeping in view the potential demands of 22 nm (and beyond) technology nodes for high-k dielectric materials, the device reliability was taken into consideration by selecting appropriate atomic scale deposition techniques and device characterization methods. This paper presents the fabrication of n-Si/ALD-ZrO₂ gate stack with an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL). The problem of the gate leakage current has been resolved by post deposition annealing (PDA) of ZrO₂ film ~ 11.63 nm in oxygen ambient on the silicon substrate followed by the pre-growth of SiON IL ~ 6.92 nm. The structural, morphological and film thickness studies have been performed by the characterization techniques such as XRD, AFM and FESEM respectively. Electrical characterizations such as capacitance-voltage (C-V) and current density-voltage (J-V) reveal the improved results for O₂ annealed ZrO₂ sample relative to the as-deposited ZrO₂ sample in terms of suppressed gate leakage current (~ 2.8 × 10^-8 A/cm²), increased dielectric constant (~ 33) and reduced effective oxide thickness (EOT~ 1.37 nm). Furthermore, in this paper, we will present comparative studies on types of gate stacks viz. HfO₂/SiO₂, HfO₂/SiON, Ar-annealed ZrO₂/SiON, N₂ annealed ZrO₂/SiON and O₂ annealed ZrO₂/SiON and their comparative analysis indicates better results for O₂ annealed ZrO₂/SiON in terms of reduced EOT, reduced leakage current and increased dielectric constant.