High-mobility channel materials are important to extend the CMOS technology to beyond 3-nm node. GeSn p-MOSFETs with a record-high hole mobility of 845 cm²/V-s and a high drive current of > 1850 A/m were demonstrated [1, 2]. While the high-performance GeSn p-FETs were demonstrated, the required complicated fabrication steps remain challenging. A junctionless (JL) FinFET device was proposed to suppress the short-channel effects with easier fabrication steps [3]. Furthermore, for the JL devices, there are no additional ion implantation or annealing steps for the S/D formation, which can prevent Sn segregation or strain relaxation. While the device performance of JL FinFETs can be enhanced by increasing the channel doping concentration, the electrostatic control over the bulk channel in a JL FinFET becomes worse. In this work, we address the effects of the fin width and doping concentration on the device performance of GeSn JL FinFETs.

GeSn JL p-FinFETs with fin widths of 10–50 nm are fabricated (Fig. 1 (a)). High-quality p-GeSn films were epitaxially grown on silicon-on-insulator substrates by in-situ doping chemical vapor deposition (CVD) and . HR-XRD results showed that the Ge_0.92Sn_0.08 layer was fully strained to the underlying relaxed Ge layer with clear Pendellösung fringes around the GeSn peak. Excellent crystallinity and defect-free GeSn/Ge interface can be observed in TEM images. The carrier density and mobility were characterized by Hall measurements. Boron dopants were fully activated up to the level of 1.3 × 10¹⁹ cm^-3. The device fabrication steps were carried out at temperatures below 400 ^◦C to prevent the Sn segregation. After a post-metal annealing step, the drive current was boosted by a factor of 1.5 due to the reduction of the contact resistance by the NiGeSn formation (Fig. 1 (b)). Furthermore, the SS was also improved after the PMA step. To improve the device performance of JL FinFETs, the doping concentration in the GeSn channel was increased by in-situ CVD. The drive current increases with the doping concentration due to the larger channel conductivity (Fig. 1 (c)). Benefiting from the low-temperature processes, JL structure, and the narrow fin width, the best SS is 88 mV/dec and extremely high I_on/I_off ratios of 10⁵ and 10⁷ were achieved for the overdrive voltages of 0.7 V and 2 V, respectively (Fig. 1 (d)).

Last, TCAD simulations were performed to investigate the effects of the channel doping concentration, the fin width, and the defect density at the oxide interface on SS. While for a high performance GeSn JL FinFET, the doping level was increased, the channel cannot be shut off effectively, leading to a higher subthreshold leakage and a poorer SS. To effectively deplete the carriers in the channel, a much reduced fin will be required. While shrinking the devices could improve the SS, the simulation results suggest that reducing the defect density at the high-k/GeSn interface is also crucial for further performance improvements of the GeSn JL FinFETs.

[1] M. Liu et al., VLSI Symp. Tech. Dig., Jun. 2014.

[2] Y.-S. Huang et al., IEDM Tech. Dig., Dec. 2017.

[3] J. Colinge et al., Solid-State Electron., vol. 65, pp. 33–37, Nov. 2011.