The Thermal Characteristics of AlGaN/GaN Hemts with Different Channel Width

Tuesday, 15 October 2019
Grand Ballroom (The Hilton Atlanta)
W. C. Lin, Y. N. Zhong, M. Y. Tsai, W. C. Ho, Y. H. Yu, and Y. M. Hsin (National Central University)
In this study, the thermal characteristics of AlGaN/GaN HEMTs with different channel widths were investigated. The thermal characteristics including threshold voltage, maximum transconductance (gm,max), on-state current, and on-resistance were investigated from 30 to 150 °C with the increment of 10°C. All devices have the same source, gate and drain widths, but difference in the channel widths. The channel width (Wchannel) is determined by a current blocking region between the source and drain. Device A is a conventional device with gate width (WG) of 50 mm without the current blocking region. Therefore, the channel width is the same as the gate width. Device B, C, and D have the gate width of 50 mm but different channel widths of 27.5, 25, and 12.5 mm, respectively. The dimension of the channel width was implemented by ion-implantation at the process step of device isolation. All epitaxial layers were grown on Si substrate. All devices were passivated by a 200-nm PECVD SiN without field plates. The devices under test are with a gate-source distance (LGS) of 4-µm, a gate length (LG) of 2-µm, gate width (WG) of 50-µm, and a gate-drain distance (LGD) of 10-µm.

At room temperature, device B, C, and D with smaller channel widths show the improved on-state current density, subthreshold swing, and gm. Device D shows a gm,max of 239 mS/mm compared to the 127 mS/mm of the device A. A significant improvement was observed in gm,max of device D due to the large ratio of WG/Wchannel. A better capability of the gate control is achieved. However, the thermal characteristics show the opposite trend. The measured thermal coefficients of the threshold voltage, gm,max, on-state current, and on-resistance of the device D are 2.1´10-4, -6.7´10-3, -3.4´10-3, and 1.1´10-2 1/°C compared with 1.5´10-5, -1.4´10-3, -2.1´10-3, and 7.2´10-3 1/°C of the device A. The possible reason is due to the current crowding at the corners of the blocking region. A suitable heatsink design or back side via are required to reduce the thermal impact.