G03 - Advanced Post CMOS Devices and Processes

Monday, 14 October 2019: 14:00-15:30
Room 211 (The Hilton Atlanta)
Chairs:
Eddy Roger Simoen and Oussama Moutanabbir
14:00
(Invited) Tunneling FET Device Technology for Ultra-Low Power Integrated Circuits
S. Takagi, K. Kato, D. H. Ahn, T. Gotow, R. Takaguchi, T. E. Bae, K. Toprasertpong, and M. Takenaka (The University of Tokyo)
14:30
(Invited) Vertically Stacked n Channel and p Channel Transistors
C. W. Liu (National Taiwan University, Taiwan Semiconductor Research Institute), Y. S. Huang, F. L. Lu, and H. Y. Ye (National Taiwan University)
15:00
(Invited) Vertical Tunneling FET Technologies Using III-V/Si Heterojunction
K. Tomioka (GS-IST, RCIQE, Hokkaido University), H. Gamo (GS-IST, RCIQE, Hokkaido Unviersity), and J. Motohisa (GS-IST, RCIQE, Hokkaido University)
See more of: G03: Semiconductor Process Integration 11
See more of: Electronic Materials and Processing
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