It is well known that compressive strain is effective in improving pMOSFET performance. We have long been working on improving the performance of ultra-thin GOI pMOSFETs [1-5] formed on Si substrates using the Ge condensation method [6]. By optimizing the condensation process, inserting an annealing step, slowing the temperature cooling rate after the condensation is completed [1], and reducing the SiGe film thickness of the initial substrate, we have achieved high quality GOI films with 1.75-time-higher compressive strain [2, 3]. This high strain does not relax even after thinning down to about 3 nm. Clear device operation has been confirmed even for 2-nm-thick GOI pMOSFETs, which were thinned down by the digital etching method [7]. Although a decrease in mobility is observed with reducing the film thickness, the introduction of compressive strain can lead to a significant increase in mobility even in the extremely-thin film region. Also, the mobility in pMOSFETs is known to be further improved by using uniaxial compressive strain rather than biaxial compressive strain [8]. Therefore, we introduced quasi-uniaxial strain by patterning the biaxial-strain GOI structure into narrow wire shapes and relaxing the strain along the channel width direction, which can introduce highly uniaxial compressive strain along the <110> direction [4, 5]. It has been experimentally shown that this asymmetric strain can further improve the hole mobility in GOI pMOSFETs, attributable to the reduction of effective mass [4, 5].
On the other hand, tensile strain is effective in improving the electron mobility of nMOSFETs. Recently, we have found that, by continuing to oxidize the condensation GOI substrate with compressive strain, the strain changes from compressive to tensile one, resulting in an increase in electron mobility of fabricated GOI nMOSFETs [9, 10]. Such a technology to control strain condition of GOI channels is promising for realizing future GOI CMOS.
In addition, an ultrathin (111) GOI channel is also expected for high performance ultrathin nMOSFETs [11-13]. In order to realize this device, (111) GOI wafers on Si substrates were realized by using the smart-cut technology [14-16]. High quality (111) GOI substrates can be achieved by choosing appropriate annealing temperatures. (111) GOI nMOSFETs fabricated on this substrate have been found to have higher electron mobility than (100) GOI ones, as previously found on bulk Ge substrates. The high electron mobility is expected even in ultra-thin films less than 10 nm, as theoretically predicted, by improving interfacial properties at the bonded interface.
This work was supported by JSPS KAKENHI (17H06148, 22H00208), and Nanotechnology Platform project by MEXT (JPMXP09A20UT0046), Japan.
References [1] W.-K. Kim et al, Symp. on VLSI tech, T124, 2017 [2] K.-W. Jo et al., Symp. on VLSI tech, 195, 2018 [3] K.-W. Jo et al., Appl. Phys. Lett. 114, 062101, 2019 [4] C. T. Chen et al., Symp. on VLSI tech, T3, 2021 [5] C. T. Chen et al., IEEE Trans. Electron Devices 69, 25, 2022 [6] S. Nakaharai et al., Appl. Phys. Lett. 83, 3516, 2003 [7] X. Yu et al., IEDM, 20, 2015 [8] W. Chern et al., IEDM, 387, 2012 [9] K.-W. Jo et al., IEDM, 673, 2019 [10] X-Y. Han et al., Jpn. J. Appl. Phys. 61, SC1027, 2022 [11] S. Takagi, Symp. on VLSI tech, 115, 2003 [12] S. Takagi et al., Jpn. J. Appl. Phys. 50, 010110, 2011 [13] K. Sumita et al., IEDM, 406, 2021 [14] C.-M. Lim et al., AIP Adv. 10, 015045, 2020 [15] C.-M. Lim et al., IEEE Electron Device Lett. 41, 985, 2020 [16] C.-M. Lim et al., IEEE J. Electron Device Soc. 9, 612, 2021