With the development of the FinFET process, the impact of high-k materials (HK) on the electrical reliability of the device becomes more and more significant. Meanwhile, the replacement metal gate Bottom Anti-Reflection Coating (BARC) opening process is becoming increasingly critical in semiconductor manufacturing for multi-V_t formation. A study found that different BARC opening processes have various types of damage to the HK on the fin top, which is related to different degrees of loss of the protective layer (TaN) on HK during the BARC opening process as shown in Fig. 1a and Fig. 1b. In this paper, the effects of different etching parameters (including bias power, source power, pressure, H2/N2 ratio, the duty cycle of pulsing, and temperature) on BARC etching rate and the loss of Ta atoms were studied, and it was found that there was a significant linear relationship between the Ta atoms loss and the etching rate as shown in Fig. 1c. The experimental results show that the BARC etching rate has a positive linear correlation with bias power, source power, the duty cycle of pulsing and temperature, and a negative linear correlation with pressure. In the cases with a certain bias, changing other parameters will lead to changes in the etching rate, and the loss of Ta atoms increases by 730 atoms/cm² for every 1 A/min increase in the etching rate. In addition, when other parameters are fixed, changing bias will also lead to changes in the etching rate, and the loss of Ta atoms increases by 880 atoms/cm² for every 1 A/min increase in the etching rate. The more loss of Ta, the lower reliability of HK, which eventually leads to lower device performance, such as lower Q_bd and degradation of the gate current leakage. To reduce the fin top damage caused by Ta loss, this paper designs a series of experiments based on the orthogonal uniform design algorithm. All experimental points are scattered uniformly over the feasible solution space to ensure that the algorithm can scan the feasible solution space evenly once to find the optimal solution. Based on the DOE method of uniform design, this paper finally determines the optimal etch condition that minimizes Ta atoms loss, which will improve device reliability for advanced FinFET process nodes.