Over the past decade, the demands for 3D NAND flash memory devices have been increased tremendously due to ever growing digital economics in consumer electronics, data centers, IOT, healthcare and automotive industries. The growth is further accelerated during the recent Covid period. The industry was able to keep up the scaling roadmap by stacking more memory cell in vertical direction to realize higher bit density at reducing cost per Gig-bit.

Unlike devices scaling via feature size reduction, 3D NAND flash vertical stack scaling puts challenges mostly on film deposition and etch. Among many steps, high aspect ratio (HAR) ONON channel hole formation modules remained the most critical steps. Forming billions of perfect channel holes from top to bottom without distortion and twisting is the grand challenge. Besides individual etch and deposition module optimization, deposition and etch Co-optimization (DECO) could provide new opportunities. In this paper, we will present a summary of the recent progress in the approaches and the benefits of DECO as potential pathways to overcome the HAR ONON patterning. We will discuss the ONON Tier Optimization for profile control to reduce the top bowing and enlarge the bottom CD. We will introduce a sacrificial liner approach to prevent top CD enlargement at deeper etch depth. We will also discuss new mask materials for better etch selectivity and profile control to enable the scaling roadmap.