The dimensional scaling of the back-end of line (BeOL)interconnects is a significant challenge for the deposition and fill of conductive metals in narrow lines and small vias that are needed to connect the semiconductor devices. Especially at the lower and the smaller interconnect levels, the scaling of the copper (Cu) dual damascene is becoming the limiting factor due to the increase in the resistance-capacitance delay. The increase in RC delay results in a degradation of the chip performance. So, while the scaling in the logic device landscape leads to a continuous improvement of the device performance and an increased transistor density, the Cu wiring in the interconnects systems tend to perform worse when scaling down the dimensions. This paper addresses methodologies to continue the scaling of the BEOL interconnects down to small CD’s like 12nm. For this, process and materials innovation are the key to reduce the interconnect area and its resistance.[1] Examples that will be discussed include Cu hybrid metallization and the use of new conductor materials or integration methodologies like metal patterning.

In being the workhorse for building multilevel interconnects, the first desired direction is to push and extend the conventional Cu dual damascene metallization to small dimensions. However, extending Cu is not only challenging from a metal fill point of view, but also from the resistance as well as reliability point of view. The ideal metal that could replace the conventional Cu should have a low electrical resistance in scaled dimensions, have a good thermal conductivity, is resistant against oxidation and possesses a high melting point.[2] This melting is a good measure for the ease of electromigration due to metal diffusion where a high melting point would allow for a reliable operation without the need for a barrier material to prevent it to diffuse. This brings Ru, Mo and W in the picture as interesting material to replace Cu in the vias, and potential later in the lines as well. Figure 1 (left) shows the tabulated via and line resistance predictions for Cu and alternative metals to Cu like Co, Ru, Mo and W (method described elsewhere [3]). The red color coding is used to indicate too high resistance values, where green indicates the desired target resistance. The resistance benefit for the use of Ru, Mo or W compared to Cu is clearly visible in the table. An efficient way to introduce a new alternative metal in the Cu interconnect metallization without being too disruptive is using a selective metal deposition for the vias landing on the exposed bottom metal (Fig.1 middle). After the vias are filled using a selective metal-on-metal deposition with a barrierless metal like Ru or W [4,5], the remainder of the structures can be filled using the conventional Cu metallization scheme. This process is called a Cu hybrid metallization scheme. Filling the vias before the Cu line metallization, improves the process window and yield for the Cu gapfill. Challenges for the selective deposition of metals in vias will be discussed. The XTEM in Figure 1 (right) shows a successful example of the metal prefill in a via hole with bottom CD of 14nm. The via is nicely filled with the metal while the top lines in the dielectric that are not connected to vias do not show any non-selective deposition.

Even though the vias are becoming more and more critical in the signal routing on a system-on-chip level, the resistance penalty for the Cu lines is unacceptable at small CDs as can be seen in the table in Fig.1. But eventually, the Cu electromigration will set the limit because at 10nm CD copper lines are not expected to meet electromigration requirements anymore [6]. This is then an inflection point to also replace the lines with alternative metals like Ru, Mo or more exotic conductors like binary metals. For these metals, the challenges in the line fill, processing, and integration will be discussed which may lead to the introduction of the so-called semi-damascene module [7] instead of using the dual damascene methodology.

[1] J. Clarke et al, IEEE VLSI 2014, p. 176
[2] D. Gall et al, J. Appl. Phys. 2016, 119, p.085101
[3] I. Ciofi et al, IEEE transactions on Electron Devices 2017, 64 (5), p.2306
[5] M.H. van der Veen et al, Proc. of the IITC 2021, S7-2
[4] M. van der Veen et al, Proc. of the IITC 2020, p.16
[6] K. Croes et al, IEDM 2018, p 5.3.1
[7] Zs. Tőkei et al, IEDM 2020, p 32.2.2