Recently hafnia based thin HfZrO₂ (HZO) ferroelectric (FE) films attract great attention for next generation low power nonvolatile memory applications. To achieve the FE phase, the non-centrosymmetric polar o-phase (space group Pca2₁) in the doped-HfO₂ films under proper mechanical stress from the capped top metal during annealing and cooling process are crucial issues. However, oxygen vacancies at the TE and FE-film interface controls the formation and degradation of stable o-phase hence causes the reliability issues, which limits the endurance performance. Therefore, insertion of a thin TiN_xO_y at the Pt and HZO interface, supposed to control the oxygen vacancy by scavenging oxygen from HZO and becoming TiO_xN_y itself might provide more in-plane stress, favors for higher stable polar o (111)- phase. A 10 nm-thick HZO (66%) or HZO (50%) layer was deposited by ALD on TiN/Si substrate. After that Pt top electrode was deposited directly on HZO (66%) (D1) by RF-sputtering. A thin TiN layer (2 nm) was deposited by RF sputtering on the HZO (66%) (D2) and HZO (50%) (D3) in the Pt/TiN_xO_y/HZO/TiN/Si structure. After that the capacitors were annealed to achieve the FE polar o- (111) phase by optimizing the annealing temperature of 400^oC. From HRTEM image, it is observed that the HZO (66%) is becoming polycrystalline in the both ferroelectric layers. Both D1 and D2 devices show excellent interface at bottom TiN/HZO film. The polar orthorhombic phase i.e. o- (111) phase in the HZO layer by using the Fast Fourier Transformation (FFT) and Inverse-FFT technique (in the red marked areas). The corresponding obtained inter-planer spacing is 2.96 Å and 2.98 Å for for the D1 and D2, respectively. The ferroelectric property is responsible due to these higher d-spacing values. Capacitance-voltage characteristics of the D1 and D2 and D3 FE devices at ±3 V, 5 kHz frequency are obtained. The dielectric constant (k) values at the cross-points are 27.5, 29 and 32.7 for the D1, D3 and D2, respectively. The corresponding 2Pr values are 14.5 µC/cm², 11.4 µC/cm² and 17 µC/cm² for the D1, D2 and D3 devices under ±4V, respectively. D3 device shows the highest average 2Pr values with compare to the D1 and D3 devices as Hf:Zr = 1:1 favors the highest 2Pr. Though the 2Pr values of D2 device is lower than D1 device but better endurance characteristic has been observed in the D2 as well as in D3 devices which is important for the practical application. The endurance cycling performance of the D1 capacitors is failed within 10⁹ cycles, however D2 and D3 devices can sustain >10¹⁰ cumulative endurance cycles at ±2.5 V, 1 MHz square wave. Furthermore, the D2 device can sustain >10¹⁰ endurance cycles and D3 device even longer >10¹¹ cycles at high electric field of 4 MV/cm, 0.5 µs pulse width. The presence of thin TiN_xO_y interfacial layer leads to significant cycling improvement. The TiN interfacial layer acts as the oxygen scavenging layer from the HZO layer and provides the higher in-plane stress during the annealing and also control the optimum oxygen vacancy at the HZO layer. Thus improves the long cycling stability. We have demonstrated, for the first time, the enhance FE performance using the thin TiN_xO_y interfacial capping layer at the Pt/HZO interface. Our device with interfacial capping layer has longer >10¹¹ cycles with sufficient Pr value, which could be beneficial for future multi-functional non-volatile memory applications.

Acknowledgments: This work was supported by Ministry of Science and Technology (MOST), Taiwan under contract numbers: 109-2622-8-002-003, 110-2622-8-002-014, and 110-2218-E-003-005.