Low Dimensional Channel Materials for Logic Transistors

Monday, 10 October 2022: 11:10
Room 212 (The Hilton Atlanta)
H. S. P. Wong (Stanford University)
A key technology future direction is CMOS + X, where X can be memory, photonics, spintronics, power electronics, nanomechanics, sensors and actuators, RF/mm-wave, and even quantum computing. Nanosystems of 3D integrated “X” technology (N3XT) is a key concept at the chip level. We must also go beyond a single chip from a wafer and focus on integrating chips into systems using MOSAIC (MOnolithic Stacked Assembled IC). I will give an overview of the new materials and device technologies that may need to be developed to realize this vision. In particular, low-dimensional materials are suitable for logic transistors in this 3D MOSAIC of N3XT chips vision because of the low temperature for device fabrication as well as the thin device layers.