Multi project-wafers (MPWs) offer cost-effective options for fabrication of application specific integrated circuits (ASICs) produced for entities not requiring a large volume of die from a dedicated full wafer run at an advanced semiconductor foundry. MPWs consist of a mixture of different devices shared on a single wafer; thereby reducing cost of processing by allowing the purchase of real estate allotted to each device. This practice is advantageous for those in academia or government that often only require small quantities of devices for research or niche applications. With many teams investing in a single wafer run, strict design rules must be followed on these microelectronic chips. In particular, the metal used in the final routing layer must be AlCu. This AlCu metallization is not compatible with solder connections for flip chip bonding applications because solder is unable to wet AlCu. To allow MPW die integration with flip chip bonding applications, a solder compatible under bump metallization (UBM) must be deposited on top of the AlCu. This UBM deposition can be achieved through physical vapor deposition and subsequent electrolytic plating into a photolithography defined plating mold. Unfortunately, photolithographic processes are only compatible with full wafers and not with singulated die. This leaves electroless deposition methods such as immersion tin or zinc followed by electroless nickel, electroless palladium, immersion gold (ENEPIG) or electroless nickel and immersion gold (ENIG) as the only options for depositing a wettable UBM on MPW die. Electroless deposition can be performed with a single die at a time, however this process is not well suited for manufacturing. In this work, we have developed a scheme for batch level UBM deposition on singulated semiconductor die by coupling temporary bonding with electroless deposition.

A unique batch approach is proposed to electrolessly deposit UBM to terminal AlCu on MPW die. Preliminary Si sidewall passivation is used to eliminate metallization of unintended surfaces in subsequent steps. Temporary custom fixturing onto a carrier substrate is leveraged allowing a variety of devices to be processed like a full wafer, establishing feasibility for industrial scaling. The bulk aluminum oxide is then solubilized by chemical etching and replaced by reduction of Sn as a base layer for ENIG and ENEPIG processes as seen in Figure 1. After metal deposition, devices are liberated from the temporary mounting substrate making them ready for flip chip bonding. Due to creating an UBM through electroless processes, options for interposer bumps are limited and outlined in Figure 2. Solder bonds from Cu pillars topped with SnAg or electroplated with either AuSn or SnAg allow a reflow solder attachment to complete electrical contact between the two chips. Electroplated Au bumps allow for a thermocompression bond to be made between the two chips. Both methods have benefits based on circumstance. Reflow solder is advantageous for fragile chips that cannot withstand the high pressure associated with thermocompression. Cu pillars are also attractive for RF devices in that Cu offers reduced electrical parisitics. Thermocompression is advantageous because it does not require high level of uniformity in the final Au bump. In this presentation, we will provide details on the passivation, batch level handling process, uniformity, and yield statistics for the electroless deposition.

Supported by the Laboratory Directed Research and Development program at Sandia National Laboratories, a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525.