The SiO₂-film chemical-mechanical-polishing (CMP) is essential process for Shallow Trench Isolation (STI) and Inter Layer Dielectric (ILD) CMP. The key performance parameters are high polishing rate and scratch-less in SiO₂-film CMP. In SiO₂-film CMP, wet-ceria was widely used for scratch-less SiO₂-film CMP. However, the wet-Ceria abrasive has crystalline sharp <100>, <100>, and <111> facet, which resulted in generating scratches on SiO₂-film by stick and slip mechanism after SiO₂ CMP, as shown in Fig.1. Thus the scratches induced by wet-ceria abrasives can be a major cause of poor device operation and yield drop in the memory device manufacturing. In our study, therefore, we designed a novel SiO₂-film CMP slurry using the PS/ceria core/shell as an abrasive to enhance SiO₂-film polishing rate and scratch-less after SiO₂-film CMP.

PS/ceria core/shell particles were synthesized, which are relatively soft and round by using polystyrene and ceria particles. Figure 2(a) shows the synthesis mechanism of PS/ceria core/shell, illustrating that Ce⁴⁺ ion was added in the PS of negative charge to form Ce⁴⁺ seed on the surface and grow it during 7 h with 70 ℃. The TEM image of the synthesized PS/ceria core/shell was shown in Fig. 2(b). First, we investigated the polishing rate of SiO₂-film using PS/ceria core/shell abrasives. The polishing rate of SiO₂-film was 564 Å/min when using PS/ceria core/shell and 350 Å/min when using wet-ceria as abrasives, as shown in Fig.3. This result means that the real contact area of PS/ceria core/shell is larger than that of 70 nm size wet-ceria. Second, we measured the surface roughness [root-mean-square (RMS) at 10 x 10-um scanning area] of SiO₂-film and the surface defect such as scratch after CMP. The surface roughness of SiO₂-film was 0.327 nm using wet-ceria and 0.202 nm using PS/ceria core/shell, respectively, as shown in Fig. 4(a). The number of scratch was 51-ea in 10-mm² area and the deepest depth of scratch was 18 nm using 70 nm size wet ceria. However, the number of scratch was 10-ea in 10-mm² area and the deepest depth of scratch was 2.3 nm using PS/ceria core/shell, as shown in Fig. 4(b). These results indicate that the hardness of PS/ceria core/shell is smaller than that of 70 nm size wet-ceria. In our presentation, we will review the mechanism for improving CMP performance such as high polishing rate, low surface roughness and scratch-less after CMP when using the PS/ceria core/shell abrasive based slurry.

* This research was supported by the MOTIE(Ministry of Trade, Industry & Energy (10085643) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. This work was financially supported by the Brain Korea 21 Plus Program in 2018 and Research & Business Development Program Announcement funded by the MOTIE (N0002026).