Device Physics and Simulations-3

Tuesday, May 14, 2013: 16:20-18:30
Dominion Ballroom North, Second Floor (Sheraton)
Chairs:
Jean-Pierre Raskin and Yasuhisa Omura, Ph. D
16:20
896
Tunnel FETs for Mixed-Signal System-On-Chip Applications
Abhijit Mallik, Ph.D., University of Calcutta
17:00
897
Dopant-Free CMOS on SOI: Multi-Gate Si-Nanowire Transistors for Logic and Memory Applications
Udo Schwalke, Prof. Dr., Technische Universität Darmstadt, ISTN; Tillmann Krauss, Dipl. Ing., Technische Universität Darmstadt, ISTN; Frank Wessely, Dr.-Ing., Technische Universität Darmstadt, ISTN
17:20
898
Performance of Junctionless Nanowire MOSFET as a Quasi-Linear Resistor
Michelly de Souza, PhD, Centro Universitario da FEI; Rodrigo Trevisoli Doria, PhD, University of São Paulo; Renan Doria Trevisoli, MSc, Centro Universitario da FEI; Antonio Cerdeira, PhD, CINVESTAV-IPN; Magali Estrada, PhD, CINVESTAV-IPN; Marcelo Antonio Pavanello, PhD, Centro Universitario da FEI
17:40
899
Operation of Lateral SOI PIN Photodiodes with Back-Gate Bias and Intrinsic Length Variation
C. Novo, Centro Universitário da FEI; R. Giacomini, Centro Universitário da FEI; A. Afzalian, Université Catholique de Louvain; D. Flandre, Université Catholique de Louvain
18:00
900
Enhancement of SOI Photodiode Sensitivity by Aluminum Grating
Hiroshi Inokawa, Research Institute of Electronics, Shizuoka University; Hiroaki Satoh, Research Institute of Electronics, Shizuoka University; Ken Kawakubo, Research Institute of Electronics, Shizuoka University; Atsushi Ono, Research Institute of Electronics, Shizuoka University
18:20
Concluding Remarks
See more of: E6: Advanced Semiconductor-on-Insulator Technology and Related Physics 16
See more of: Dielectric and Semiconductor Materials, Devices, and Processing
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