Delay-Time Effect on the Transistor Performance after Reactive Ion Etching

Since recessed channel array transistor (RCAT) was adopted from 100 nm feature size, gate-induced-drain-leakage (GIDL) has been the major cause of refresh fail. [1] The process of inner-gate-recess was adapted and GIDL in RCAT structure has been remarkably reduced by lowering electric field at overlap region. Fig.1 (a) and (b) show the VSEM image of inner-gate-recessed-RCAT and the electric field simulation, respectively. The process of recessing gate-poly was executed at both cell array transistor such as RCAT and planar transistor in logical circuits. In case of planar transistor, there was no need to recess poly-Si except SiO₂ layer. During the etching of poly-Si in the cell array, the thin oxide layer in the planar area should be preserved to prevent Si-pitting. HBr/O₂ plasma has been used to improve the selectivity of poly-Si to gate oxide in gate-stack etching. HBr/O₂ plasma produced polymer residues such as SiBr and SiBrO_x layer on the underlying gate oxide and polymer residues should be removed. [2, 3] Fig.2 shows the variation of stand-by current of DRAM and propagation time of inverter (t_PD) with wafer number in a lot investigated. Wafer number indicates the order in processing. As the number of wafer increased, stand-by current increased and t_PD decreased. Fig.3 shows the saturation current of PMOS and the saturation current also decreased with increasing wafer number. Structural analysis was evaluated, and the difference between the first wafer and the last wafer was found. There was thicker SiO₂ layer on the gate stack in the first wafer. Especially, to make the gate recessed profile of RCAT, the over-etch time increased and the exposure time in HBr/O₂ plasma also increased. It induced to increase polymer residues and unexpected SiO₂ offset spacer. As the HF removal was delayed for measuring critical dimension (CD) of gate stack and thickness of remain substrate, deposited SiBr among the polymer residues reacted with O₂ in the air and additional SiO₂ was grown. [4] The first wafer in the lot investigated had much more delay time than the last wafer. Therefore thicker SiO₂ in the first wafer was grown than that of the last wafer, and the SiO₂ in the first wafer was insufficiently removed by HF clean. SiO₂ offset made under-lap from gate to source/drain and induced increasing resistance and decreasing saturation current. [5, 6] Fig.4 (a) and (b) show the TEM profiles and explain the cause of saturation current difference obtained from the same lot. Immediate HF cleaning after gate etching was introduced and CD was measured with increasing time by the scanning electron microscope (SEM). Fig. 5 shows the CD variation monitored as a function of delay time. While SiO₂ layer was steadily grown with increasing delay time without HF cleaning, the SiO₂ and residual SiBr layer on the sidewall of gate stack were easily removed and additional SiO₂was not grown in case of immediate HF clean. As the integration process is more complicated and delicate, small variation brings the big failure. Delay time after reactive ion etching should be reduced, and immediate cleaning should be appropriately considered.

References

[1] Kim J.Y., et al., Symposium on VLSI technology Digest, 2003, pp. 11-12

[2] Deok-Kee Kim, et al., Materials Science in Semiconductor Processing, Vol.10, 2006, pp. 41-48

[3] V.M. Donnelly, et al., Applied Physics Letters, Vol.74, pp. 1260-1262

[4] Shih-Po Lin, et al., Journal of Vacuum Science & Technology A, Vol.18, 2000, pp. 1173-1175

[5] B. J. Sheu, et al., IEEE Electron Device Letter, Vol. 5, 1984, pp. 365-367

[6] J. Lee, et al., IEEE Electron Device Letters, Vol. 7, 1986, pp. 152-154