(Invited) Development of Novel Three-Dimensional Structuring of Integrated Circuits by Using Low Temperature Direct Bonding for CMOS Image Sensors

Tuesday, May 13, 2014: 15:20
Union, Ground Level (Hilton Orlando Bonnet Creek)
M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake (NHK Science and Technology Research Laboratories), T. Saraya, E. Higurashi, H. Toshiyoshi, and T. Hiramoto (The University of Tokyo)
Recent demands are escalating for higher density of 3D ICs. Stacked CMOS image sensors [1], for example, reduce their pixel footprints down to a few μm2, and interconnection between individual FETs on different layers is needed to integrate 3D ICs into such a small area. Various approaches of 3D IC have been reported, as listed in Table 1 [2-4]. Although through silicon via (TSV) approaches are most common [2], it is unsuitable for local interconnection due to its large diameter (> 5 μm). Approaches based on the sequential integration [3] and silicon-on-insulator (SOI) assembly [4] are also promising. However, penetrating vias for interconnection are required outside the FET areas, limiting the density and free wiring layout.

To overcome these problems, we have developed a novel 3D structuring process as shown in Fig. 1. In this process, (a) FETs were formed on the FD (fully-depleted) SOI wafers [5]. (b) Intermediate SiO2 layer was patterned, and Au layer was formed by electroplating. (c) Damascene process by chemical mechanical polishing (CMP) was applied to form Au/SiO2 hybrid surface. (d) After chip-dicing into a 20-mm-square size, Ar and O2 plasma were sequentially performed for surface activation. (e) Two chips were directly bonded at a force of 2000 N for 60 min at 200 °C. Fig. 2 (a) shows the photograph of the Au/SiO2 surface after CMP. Average roughness of the SiO2 was 0.15 nm. Minimum diameter of the Au bonding electrodes was 3 μm. Fig. 2 (b) shows the cross-sectional image, where no void in bonded interface is observed.

To demonstrate the availability of the 3D structuring, a 3D CMOS inverter was developed, where NFET and PFET in separate layers were bonded to each other as illustrated in Fig. 3, which reduced circuit area. As this method separates the NFET and PFET processes, both processes could be optimized independently in respective wafers, enabling us to make ideal channels for NFET and PFET in the advanced CMOS processes.

Experimentally obtained characteristics of the developed 3D CMOS inverter with 3-μm-diameter Au electrodes are shown in Fig. 4. The figure compares the results with those of the 2D chip developed at the same time, which confirms that the bonding gives no degradation in the IC performance. To confirm the yield of interconnection bonding, a 3D ring oscillator with 101 stages of CMOS inverters was also developed from the NFETs and PFETs made on separate wafers. Oscillation frequency at 1.8 V was observed at 700 kHz as shown in Fig. 5.

In summary, 3D structuring technology with excellent suitability for high-density integration was successfully demonstrated by applying Au/SiO2 hybrid bonding. The developed process is promising for the highly integrated stacked CMOS image sensors and More-than-Moore type devices for the next generation.


[1] J. Aoki et al., ISSCC 2013, pp.482–483.

[2] G. Katti et al., IEDM 2009, pp.357–360.

[3] P. Batude et al., IEDM 2011, pp.151–154.

[4] A. W. Topol et al., IEDM 2005, pp.352–355.

[5] M. Goto et al., ECS trans., 50 (14), pp.49–54, 2013.