(Invited) Terahertz CMOS Electronics for Future Mobile Applications

Monday, May 12, 2014: 14:00
Union, Ground Level (Hilton Orlando Bonnet Creek)
M. Fujishima (Hiroshima University)
The highest operation frequency of RFCMOS circuits has risen exponentially over the years. This improved performance has culminated in new wireless and wireline communication standards with higher data rates. There has been a tenfold increase in the wireless data rate every four years, being much faster than the increasing speed of wireline communications. If this trend is to continue, 100 Gb/s will be realized around 2020. In order to realize a terahertz CMOS transceiver with 100 Gb/s, not only is device performance improvement through miniaturization important, but also circuit design techniques that move the circuit operation frequency close to fmax must be developed. Furthermore, one has to remind that stringent practical issue, power consumption, still remains for mobile applications even if the terahertz transceiver is technically feasible. Namely, one must consider how the power consumption maintains at the level of the current mobile applications even when ultrahigh data rate is acquired. This challenging issue implies that the near-fmax design technique is extremely useful because the fmax of a given MOSFET is a function of bias voltage, and reduced-fmax circuits can have superior power efficiency.

 To utilize near-fmax technology, firstly, one has to know the optimum bias point giving maximum operation frequency under limited power consumption. To achieve low-power operation at a high operation frequency, it is important to choose an appropriate set of bias voltages. The FP (frequency-power) plot is a useful guide to choosing such a set, which shows the gate and drain bias dependences of fmax and power consumption per unit gate width of an NMOSFET. The power-efficient bias points can be found from the FP plot as the points on the power contours where fmax is maximized. The power-efficient bias points give the best fmax for the given power consumption. Since the highest possible fmax of a given MOSFET is realized away from the power-efficient bias points, it is best to avoid the bias point that maximizes the transconductance (gm) if power efficiency is an important design goal. By reducing the actual fmax to be used through tracing the power-efficient bias curve, power consumption can be reduced considerably. As can be observed in 65- and 40-nm CMOS processes, reducing fmax enables exponential power reduction, where the reduction rate is 1/10 every 75 GHz in both process technologies.

 When trying to obtain the highest possible performance of a MOSFET, the MOSFET must be biased such that its highest fmax is realized. If, on the other hand, the power consumption is a great concern in a terahertz mobile application, one can opt for a reduced-fmax design. Power-efficient bias points can be found in the FP plot. Continued improvement of the device performance is thus essential for achieving the ultimate low-power high-speed wireless communication even in mobile application.