(Invited) Terahertz CMOS Electronics for Future Mobile Applications
To utilize near-fmax technology, firstly, one has to know the optimum bias point giving maximum operation frequency under limited power consumption. To achieve low-power operation at a high operation frequency, it is important to choose an appropriate set of bias voltages. The FP (frequency-power) plot is a useful guide to choosing such a set, which shows the gate and drain bias dependences of fmax and power consumption per unit gate width of an NMOSFET. The power-efficient bias points can be found from the FP plot as the points on the power contours where fmax is maximized. The power-efficient bias points give the best fmax for the given power consumption. Since the highest possible fmax of a given MOSFET is realized away from the power-efficient bias points, it is best to avoid the bias point that maximizes the transconductance (gm) if power efficiency is an important design goal. By reducing the actual fmax to be used through tracing the power-efficient bias curve, power consumption can be reduced considerably. As can be observed in 65- and 40-nm CMOS processes, reducing fmax enables exponential power reduction, where the reduction rate is 1/10 every 75 GHz in both process technologies.
When trying to obtain the highest possible performance of a MOSFET, the MOSFET must be biased such that its highest fmax is realized. If, on the other hand, the power consumption is a great concern in a terahertz mobile application, one can opt for a reduced-fmax design. Power-efficient bias points can be found in the FP plot. Continued improvement of the device performance is thus essential for achieving the ultimate low-power high-speed wireless communication even in mobile application.