Sige Selective Epitaxial Growth Process for 22 Nm Node CMOS and Beyond
In order to further enhance the MOS channel mobility, the recess shape has to be designed to create maximum strain from the grown SiGe layers. To achieve this goal the etch step has been modified to elaborate a sigma (∑) shape recess and a high Ge content film is deposited in S/D regions . Then SiGe epitaxy process becomes sensitive to surface quality of the recess where a careful etching and in- and ex-situ cleaning are demanded.
In this study, selective Si1-xGex growth (0.25≤x≤0.35) with boron concentration of 1-3×1020 cm-3for 22nm node CMOS process has been investigated (see Fig.1). The selectivity issue has examined/tuned around the gate region where both nitride and oxide layers were presented and the thermal budget was decreased to 800 °C to preserve the sigma shape in the S/D regions (see Fig.2).
The structures contained two Si1-xGex layers; where the recess was filled first with Si0.65Ge0.35 and then a cap Si0.75Ge0.25layer to elevate the S/D regions. The purpose for having the elevated SiGe cap layer was to avoid strain relaxation in the SiGe bottom layer during the Ni-silicidation process.
The Ge content in epi-layers on the chips was measured directly by rocking curves (RCs) using high-resolution x-ray diffraction (HRXRD). RC were done at (113) reflection where the incident beam is as low as 2.6° and a large area of sample containing an enormous of number of transistors could be covered by x-ray beam. These RCs were simulated by the Takagi-Taupin equations and compared to the experimental curves in order to obtain the high precision data analysis. In these measurements, the boron concentration was estimated by the strain compensation in SiGe layers. The shift of B-doped SiGe peak was compared to the intrinsic ones and interpreted into the substitutional dopant concentration. In these SiGe layers, the B dopant concentration was quite high and the strain compensation could easily be measured.
Cross-section images where provided by high-resolution scanning electron microscopy (HRSEM) and transmission electron microscopy (HRTEM) to measure the layer thickness, epi-quality, and integrity of the whole transistor structures. In the latter analysis, energy dispersive spectroscopy (EDS) technique was also employed to measure the Ge profile in parallel and perpendicular directions in the S/D regions of the transistors.