Electrochemical Cell Design with Controlled Hydrodynamics for Uniform Processing

In the manufacture of printed circuit boards (PCBs), copper electrodeposition is the standard fabrication method for metallization of z-axis interconnects.^[i]  Z-interconnects are important features of the PCB as they facilitate vertical electrical connections, thus eliminating the need for long in-plane interconnects.  This in turn enables higher density feature packing and results in smaller and lighter electronic products.  This trend has significant implications for the electronics industry which must ensure that the copper electrodeposition process meets the functionality and quality requirements of these advanced device designs.  For instance, uneven localized current distribution results in thin barrel plating or voiding in the fill of the z-interconnect.  Traditionally, this has been addressed through use of additive chemistry, pulse plating, use of low current densities, surface overplate and in extreme instances reorientation of the panel during the plating process.

Faraday Technology has engineered and developed an electrochemical cell geometry^{[ii],[iii],[iv],[v]}that delivers a uniform and reproducible boundary layer thickness across an 18 x 24 inch substrate in order to promote plating uniformity for full size PCB panels.  A uniform hydrodynamic boundary layer is achieved with a novel flow scheme (Figure 1) that utilizes eductor flow to enhance solution flow velocity.  In addition to the novel flow mechanism, the cell has lateral oscillation and vibration to further improve uniformity of aggressive PCB features as well as insulating shields, which enable uniform deposition of different substrate sizes.

The development of the patented cell geometry was initiated to compliment pulse and pulse-reverse waveform development for PCB metallization.  Uniform boundary layer conditions allow the full benefits of the pulse/pulse-reverse waveform to be realized.  Pulse and pulse-reverse processes may be used with or without additive plating chemistry and improve the throwing power of the deposition process and the quality of the copper deposit as compared to DC electrodeposition at comparable current densities.  Use of pulse and pulse-reverse deposition allows control of the deposit characteristics, such as control of the grain size, which is important for thermal cycling considerations.  As such, coupling the novel cell geometry with pulse/pulse-reverse deposition provides a manufacturing solution for the continued miniaturization of electronic devices.  

The cell has been extensively characterized in terms of thickness distribution as a function of cell components, shielding dimensions and substrate dimensions.^{[vi],[vii],[viii]}  The boundary layer of the cell has been experimentally calculated revealing a uniform boundary layer across an 18 x 24 inch flat substrate.⁸  Further, the cell has been validated through the deposition of varying PCB feature dimensions, indicating the cell is an ample tool in the fabrication of PCBs.  Finally, the cell has been compared to other plating cell geometries in terms of thickness distribution, tensile strength and feature metallization.^[ix]

Uniformity of copper deposits as a function of cell components along with examples of metallized PCB features will be discussed.  Additionally, Faraday will present preliminary discussions about installation of an industrial cell based on the patented technology in a PCB manufacturing environment, demonstrating the scalability of the technology.

The authors wish to acknowledge financial support from the National Science Foundation.

 

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[i]  P. Dixit, J. Miao and R. Preisser, Electrochem Solid State Lett, 9 (10), G305 (2006).

[ii] L.E. Gebhart, J.J. Sun, P.O. Miller, and E.J. Taylor, US Patent 7,553,401 (Issued 6-3-09).

[iii] L.E. Gebhart and E.J. Taylor, US Patent 7,947,161 (Issued 5-24-11).

[iv] L.E. Gebhart and E.J. Taylor, US Patent 8,226,804 (Issued 7-24-12).

[v] L.E. Gebhart, J.J. Sun, P.O. Miler and E.J. Taylor, US Patent 8,329,006 (Issued 12-12-12).

[vi] H. Garich, L. Gebhart, S. Snyder, and E.J. Taylor, ECS Trans, 19(6), 11-18 (2009). 

[vii] S. T. Snyder, H. M. Garich, B. S. Kagajwala, and, E. J.  Taylor, Products Finishing, September 2012.

[viii] H. Garich, L. Gebhart, E.J. Taylor, M. Inman and H. McCrabb, ECS Trans, 3(16), 1-10 (2007).

[ix] J. Sun et al, Effect of Plating Cell Configuration on the Uniformity of Copper Thickness Distribution, Proceedings IPC/APEX 2005, Anaheim, CA.

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