Finfet Gate Etch Towards 16nm Node CMOS Technology
Wednesday, May 14, 2014: 16:00
Bonnet Creek Ballroom VI, Lobby Level (Hilton Orlando Bonnet Creek)
The 3D tri-gate FinFET device architecture is a key transistor scaling to 22nm node and beyond for its excellent short-channel performance. However, compared with planar transistors, it poses greater challenge in the finFET gate etch. As shown in fig.1, the etch needs to stop on top of the fin while etching further down to the STI oxide layer. Therefore, the top of fin needs to endure long time over etch without any structural damage which would adversely affect device performance. What’s more, the gate profile must be vertical and there should not be residual in the corner of gate and fin. It is not an easy task to achieve, at the same time, the three goals of vertical gate profile, no residual in the corner of fin and gate, as well as no structure damage on the top of fin, due to an unavoidable tradeoff. More specifically, vertical gate profile and no residual in the corner of fin demand strong etch function and light polymer, while no structure damage in the top of fin requires weak etch function and heavy polymer, which points to high etch selectivity of silicon to oxide layer.
To achieve good etch results, one often falls into this dilemma. As far as we know, few publicly available papers have provided satisfactory solutions to the above- mentioned problem. In this work, we deal with it.
The process of gate stack with CD below 30nm is illustrated in fig.2. Then, a HBr/O2 process in transformer coupled plasma is applied to finFET gate etch. As shown in fig.3, gate profile is vertical, fin is well protected and no residual appears in the corner fin.
In conclusion, an HBr/O2 plasma etch process of finFET gate with CD below 30nm is investigated.Through appropriate tradeoff , an etch result of vertical gate profile, no residual in the sidewall and corner of fin, no structure damage on the top of fin is achieved.