1700
Study of Hetero-Tunneling Gfet with an Ultra-Shallow Pocket Junction
Wednesday, May 14, 2014: 17:00
Bonnet Creek Ballroom VI, Lobby Level (Hilton Orlando Bonnet Creek)
G. Xu (Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China), Q. Xu, H. Yin, G. Wang, J. Liu, W. Xiong, C. Li, D. Wang, J. Li, and C. Zhao (Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences)
Because the subthreshold swing (SS) of a MOSFET is larger than 60mV/dec at room temperature, its threshold voltage cannot be very small. This limits the scaling of power supply voltage (V
DD) and the reduction of power density. Tunnel field effect transistor (TFET) can overcome this fundamental limitation, which mechanism is based in the band-to-band tunneling (BTBT). However, the drive current in TFETs is significantly lower than in MOSFETs owing to tunneling resistance which arises due to carrier tunneling. Achieving large drive current at low V
DDhas been a great challenge. Green transistor (gFET) is a novel structure TFET with a heavily doped pocket in the gate-source overlap region. The pocket junction can provide large and uniform field over a substantial area, which can offer larger drive current and steeper subthreshold swing as compared to conventional tunneling transistors. And, when the pocket junction depth becomes shallower, the drive current will be improved significantly. But study reveal that gFET is only suitable for orepation at 0.5V. To further reduce Vdd, even smaller bandgap material may be employed.
In this study, a hetero-tunneling gFET with an ultra-shallow pocket junction has been developed, as shown in Fig.1. The gFET was fabricated in a 8inch (100) silicon (Si) substrate, as shown in Fig.2. After LOCOS formation, silicon-germanium (Si1-xGex) and Si cap layer were grown on Si substrate using selective epitaxy. After source implantation, an ultra-shallower pocket is formed by using of the Ge preamorphization implantation (PAI), ultra low energy implantation and spike annealing. Si1-xGex and Si have different lattice constant. Biaxially strained will be formed in the Si1-xGex/Si heterostructures. The biaxial strain will shift the conduction and valance band energy levels of semiconductors and obtain ultra low effective tunneling bandgaps, which is helpful to get smaller tunneling length and barrier height. The same current can be obtained at lower gate voltage and drain voltage. The hetero-tunneling gFET integrated with the ultra-shallow pocket junction exhibits good electrical characteristics, such as smaller subthreshold swing, higher Ion/Ioff ratio and so on.
