(Invited) Extraction of Trap Densities in TFTs using C-V Characteristics

TFTs have been widely applied to FPDs. Amorphous-Si TFTs are representatively used for large-size televisions, poly-Si TFTs are utilized for mobile smartphones, oxide-semiconductor TFTs are newcomers promising for next-generation displays, and organic-semiconductor TFTs are possibilities expected for future printed electronics. Although many researchers investigate device structures and fabrication processes, device characterizations are also important in order to develop these TFTs. In this presentation, we will introduce the device characterizations based on low-f C-V methods and numerical analysis and results acquired for various kinds of TFTs.

Trap states are some of the main determinants of TFT performances. Although there exist many evaluation techniques for the trap states such as optical and crystallographical techniques, electrical techniques are most effective because TFTs are employed as electrical devices and only electrically active trap states during actual operations can be extracted using the electrical techniques. Furthermore, general techniques available for any kinds of these TFTs are preferable. As such techniques, we are developing low-f C-V methods conjunct with numerical analysis. The unique merit is that the charge densities and therefore trap densities are directly counted and no mobility models are necessary unlike the conventional electrical techniques.

First, low-f C-V characteristics are measured. Since the measurement f must be extremely low to ensure the quasi-static condition, the gate width must be very wide to make the capacitance large and measurement error small. If CMOS technology can be used, p/i/n-type TFTs are more favorable to make both electron and hole transportations smooth. In addition, the measurement system must be highly customized. Frequency dependence of C-V characteristics of a p/i/n-type poly-Si TFT is shown in Fig. 2. Since this frequency dependence is mainly due to the running time of the free carriers from the source-drain regions to the entire channel layer, the gate length must not be too long. Here, since the C-V characteristics almost agree when f is 1 Hz and 0.7 Hz, the C-V characteristic reaches the quasi-static condition when f is 1 Hz.

Next, surface potential (Φs) is calculated from the low-f C-V characteristic by applying Q = CV to the gate insulator. Energy band along the vertical direction in TFTs is shown in Fig. 3.

    Q=Ci(Vgs-Φs)

    dΦs/dVgs=1-(dQ/dVgs)/Ci=1-Cg(s+d)/Ci

    Φs=∫(1-Cg(s+d)/Ci)dVgs

As a result, Φsas well as its gradient at the semiconductor interface ((dΦs/dx)i) are calculated as functions of Vgs.

Afterward, we have to select a proper approximation for the spatial distribution of the trap states. In the cases of amorphous-Si TFTs, SPC poly-Si TFTs having poor film qualities, some oxide-semiconductor TFTs, and organic-semiconductor TFTs, trap states in the semiconductor films are dominant. In the cases of ELC poly-Si TFTs and some oxide-semiconductor TFTs, trap states at the semiconductor-insulator interfaces are dominant. On the other hand, in the case of SPC poly-Si TFTs having excellent film qualities, these trap states are comparable and should be simultaneously considered. In the case of ELC poly-Si TFTs, trap states at the front and back interfaces and grain boundaries should be simultaneously considered. Selecting a proper approximation, using physical equations such as Poisson equations, carrier density equations, and Gauss's law, executing numerical analysis, and fitting the calculated Φsand (dΦs/dx)i to those calculated from the low-f C-V characteristics, trap densities can be extracted. Sometimes, more complicated analyses are executed by combining other electrical characteristics such as backside C-V characteristics of TFTs equipping backside gate terminals and I-V characteristics.

Trap densities in various kinds of TFTs with a reference of crystal-Si MOSFETs are shown in Fig. 4 as examples of extracting the trap densities. First of all, the total numbers of the trap states are still higher for all TFTs than crystal-Si MOSFETs. Amorphous-Si TFT: The trap states consist of the deep states and tail states, and Gaussian states at a certain energy level often appear owing to the dangling bond. SPC poly-Si TFT: in the case of a well-fabricated SPC poly-Si TFT, the TFT characteristics are influenced by both the in-film trap densities (Dfi) owing to the micro twins principly formed during the SPC and interface trap densities (Dit) dependent on the surface treatment processes. ELC poly-Si TFT: We think that the front side and backside Dit are mainly owing to the dangling bonds, whereas the grain-boundary trap densities (Dgb) owing to the bond distortion. Amorphous-InGaZnO TFTs: Dfi just below Ec can be reduced using post annealing, which seriously influence the TFT characteristics. Poly-ZnO TFT: Dfi is strongly dependent on the process conditions such as oxygen partial pressure during sputtering of ZnO films.