Thinning the Active Layer of TFTs

Large area electronics on glass is now well established. It was and it is mainly driven by the flat panel displays industry. However, it gains more and more other markets: integration of electronics with any sensing function, electronics on any substrate, plastics and different kinds of paper. The basic device in this electronics is the Thin Film Transistor (TFT). As shown by its name, TFT is constituted by a stack of insulators and semiconductors thin films. The active material of these transistors was silicon at the beginning. Now, other active materials as organic semiconductors and metal oxides semiconductors are used.

The common characteristic of these materials is that their structure is mainly not single-crystalline. By this way, the energy band gap contains a lot of permitted states for electrons. The electrical conduction is affected by these states and then the electrical parameters of the transistors are lower than expected. For example, the subthreshold slope of the transistors is high and then they commute slowly.

Regarding the old works on SOI-MOSFETs, it can be remarked that the subthreshold slope improved in some experimental conditions when decreasing the thickness of the active layer.

In this work, after confirming this trend experimentally for as-deposited crystallized silicon based transistors, a simulation of the TFT electrical behavior is set up using the simulation tools from the software called Virtual Wafer Fab (SILVACO). Particularly ATLAS tool is used for the electrical simulation of the transistor. The simulated structure is a top-gate TFT deposited on 700 µm thick glass substrate (Figure 1). The substrate is modeled as SiO₂ material and it is grounded.

The density of permitted states inside the forbidden band-gap of the no single crystalline active layer is modeled by 4 exponentials with characteristic parameters W_TD, W_GD, W_GA and W_TA (Figure 2). This model can be considered as common for all semiconductors having disordered structure.

In the subthreshold region, the Fermi level moves with the increase of the gate voltage, inside the energy band defined by the defect density with the characteristic parameter W_GA. It moves more slowly when W_GA increases leading to an increase of the subthreshold slope as shown in Figure 3. More than this normal remark, this figure shows a decrease of the subthreshold slope when the thickness of the active layer decreases for the same W_GA. This behavior can be explained when plotting the lateral electrical field between source and active layer as a function of the thickness of the active layer (Figure 4). Without defects, the lateral electrical field, relatively to its value at a thickness of 1 µm, increases continuously when the thickness decreases improving then the rate of the channel formation. With defects, the lateral field stays very low when decreasing the thickness of the active still 200 nm, then it increases highly by a factor 10⁴. Comparatively it increases only by a factor 4 when the active layer is free of defects. This behavior demonstrates the beneficial effect of reducing the thickness of the active layer. This effect is more important when the active layer is defected as in no single-crystalline semiconductors.

The other beneficial effect is on the influence of the rear interface, particularly on the known back channel formation that is an important drawback for TFTs. Figure 5 shows the effect of increasing the surface charge at the rear interface for a thin and a thick active layer. The use of thin layer reduces the effect of these charges keeping low the off-current.