(Invited) A Bottom-up SiNW AMOSFET Fabrication Approach Giving SOI Level Performance

The majority carrier accumulation-mode metal-oxide-semiconductor field effect transistor (AMOSFET)^1~7 is of interest for transparent conductive oxide and silicon transistor applications. It is a very simple structure which has been shown to  provide useful on/off current ratios and subthreshold slope values.^1~6 One approach to fabricating these devices using Si has been to employ conventional top-down semiconductor processes and the use of silicon-on-insulator (SOI) substrates.⁵ We have developed bottom-up Si nano-wire(SiNW) processing  and demonstrated two versions: grow-in-place extruded and grow-in-place encapsulated SiNW approaches.^1~4,6 Both utilize Au (1) as a sacrificial material whose removal by wet etching defines the empty growth channel and (2) as the catalyst at the end of the empty channel for driving  vapor-liquid-solid (VLS) SINW growth down the empty channel.^1~4,6 In the extruded process, SiNWs emerge from the channel for subsequent transistor fabrication whereas in the encapsulated case the SiNWs remain in the channel for subsequent transistor fabrication. In both approaches, p-type Au self-doping, which is not problematic for a majority carrier device^1~4,6  is employed.  The extruded approach has dimension and growth direction control issues whereas the encapsulated approach is subject to contamination arising from the wet-etch removal of the channel-defining sacrificial Au.^1~4,6

In this report we present a new variation of the encapsulated grow-in-place approach which eliminates reactant or byproduct growth channel contamination issues. This is accomplished by employing PECVD amorphous silicon (a-Si:H) and XeF₂ as the  sacrificial material and  etchant, respectively. In this new approach, once the growth channels are formed after removing a-Si:H, the catalytic Au is deposited at one end of an empty channel giving the added advantage of control over the amount of Au used for catalysis  and doping.

After the growth of encapsulated SiNWs using the new approach, AMOSFETs were fabricated. In this demonstration, we undertook the fabrication with SiNW dimensions of 40nm in height and 100nm in width. A 10nm thick thermal SiO₂ was grown in situ at exposed areas of the SiNWs for the gate electrode and two Ohmic contacts were added directly onto other exposed areas of the SiNWs (Fig 1), using photolithography for simplicity.  The width of these contacts was 2um and the spacing between them was 3um (Fig. 2). The SiNW AMOSFETs fabricated by the new encapsulated SiNW approach gave position control and much better device performance than that seen for the previous encapsulated SiNW approach. The resulting on/off current ratio was 10⁶ and the subthreshold slope was an outstanding ~90mV/dec. These results are comparable to typical bulk MOSFETs (~70mV/dec)⁸ and the AMOSFETs fabricated by the top-down approach using SOI material (64mV/dec).⁵

 

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