Unipolar CMOS Logic for Thin-Film Transistor Technology

For most thin-film transistors, it is very difficult, if not impossible, to fabricate CMOS circuits because of the difficulty in realizing both p-type and n-type channels in the same thin-film semiconductor, despite the well-known advantage of CMOS circuits’ lower stand-by power.

The operating principle of the proposed unipolar logic circuits will be described in the context of both the double-gate transistor architecture and the single-gate transistor architecture. 

Figure 1 shows a circuit diagram for a two-input unipolar NOR and OR logic gates based on all n-channel MOSFETs, and Fig. 2 shows a circuit diagram for a two-input unipolar NAND and AND logic gates, also based on all n-channel MOSFETs. 

Figure 3 shows a schematic diagram of the possible implementation of a unipolar NAND and AND circuits based on the IGZO thin-film transistor double-gate architecture, and Fig.4 shows its counterpart based on single-gate architecture. 

The unipolar logic circuits typically suffers from the “threshold voltage loss” problem at the “HIGH” output, and we have developed a novel bootstrapping block to restore the voltage for the “HIGH” output.  Examples will be presented to show the effectiveness of the bootstrapping circuits. 

The power savings resulting from the unipolar approach as compared to its conventional counterparts will be shown by the use of simulation.  

This work has been partially supported by the  

Sandia National Laboratory  PO#1383897.