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(Invited) Single Dislocations as Nanostructure Devices: Physics and Applications
The structure and properties of dislocations in silicon have been studied for more than five decades by numerous analytical technics. Introducing dislocations into electronic devices result in significant effects on device parameters. A detrimental effect was proved if dislocations are generated in an uncontrolled manner by high-temperature treatments during processing. Therefore they are avoided. A beneficial effect, however, is obtained if dislocations are generated far from device active areas. This effect is used, for example, as internal gettering of impurities. Furthermore, measurements on individual dislocations exhibit several extraordinary optical and electronic properties. For instance, an increase of the electrical conductivity of about four orders of magnitude compared to that of bulk silicon was measured along dislocations. If these distinguished properties are usable, MOSFETs with dimensions below 10 nm and high ION currents are feasible. Their realization, however, requires the defined and reproducible generation of dislocation arrays. The present paper describes a technique to generate defined dislocation arrays, summarizes new results about the properties of individual dislocations, and demonstrates the effect of dislocations on the performance of devices.
A smart technique to realize two-dimensional arrays of dislocations is semiconductor wafer direct bonding. The technique allows one not only to control the type of the dislocations in the array, but also to adjust the distance between defects making it possible to analyze individual dislocations. In addition, the realization of dislocation arrays in thin SOI layers eliminates the interaction with bulk defects.
Measurements on a few or individual dislocations proved their extraordinary properties caused by the nanowire behavior. Fig. 1 shows the electroluminescence spectrum of a pn-LED with dislocations at room temperature. The D1 to D3 lines in the spectrum represent the strong radiative recombination by dislocations, while band-to-band (BB) excitation is suppressed by using thin SOI layers. Previous investigations showed that the appearance of the D-lines depends on the dislocation type making it possible to configure mono- or polychromatic light emitters. Moreover, the wavelengths of the D-lines between 1300 nm and 1550 nm, their reasonable efficiency, and CMOS-compatible fabrication qualify dislocation networks as promising candidates for silicon-based, on chip light emitters for optical data communication.
The incorporation of dislocations in the channel of SOI MOSFETs, Tunnel-FETs, and pn-diodes enables a detailed characterization of electronic properties of the defects. Because dislocations are parallel to <110>- directions, they are parallel to the channel orientation and source and drain form direct contacts.
An increase of the drain current (ID) by a factor of 50 is obtained if dislocations are present in the channel of nMOSFETs (Fig. 2). This suggests a preferred electron transport along dislocations. Decreasing the number of dislocations result in an exceptional increase of ID. A current density of J = 3.8∙1012 A/cm2 is measured for a single dislocation, which is consistent with a resistivity of r = 1∙10-8 Wcm. This corresponds to supermetallic properties of dislocations. Reasons of the exceptional behavior are discussed in combination with 2- and 3-dimensional device simulations using classical and quantum mechanical simulation paths.
Further details about the electronic properties of dislocations are obtained by low-temperature measurements. The existence of a 1-dimensional electron gas on dislocations is proved. This, for instance, is the reason for Coulomb blockades characterizing single electron transitions.
Concepts of the use of the exceptional electronic properties of dislocations in nanometer-scaled devices are figured.
