Electrochemical Capacitors Fabricated Using Porous Silicon

Wednesday, 8 October 2014: 10:10
Sunrise, 2nd Floor, Star Ballroom 1 (Moon Palace Resort)
D. S. Gardner, C. W. Holzwarth III, Y. Liu, S. B. Clendenning, W. Jin, Z. Chen, B. K. Moon, E. Hannah (Intel Corporation), C. Pint (Intel Corporation, Vanderbilt University), E. Mäkilä (University of Turku), C. Chen, C. Wang (Florida International University), and J. Gustafson (Intel Corporation, Ceranovo)
Electrochemical capacitors based on porous silicon nanostructures were prepared and studied. Capacitors are favored over batteries for certain applications because they can provide higher power, albeit at lower energy densities, and do not degrade significantly over many thousands of charging cycles. These properties are a direct result of the fact that capacitors do not rely on chemical reactions to store energy. In this work, measurements from the porous silicon capacitors reveal that high capacitance can be achieved contrary to previously reported early studies [1, 2]. The devices were fabricated using silicon process methods with the potential to be incorporated into integrated circuits.

Porous silicon nanostructures having extremely high surface-to-volume ratios with channel sizes 20 nm to 100 nm were combined with an ionic electrolyte to create an electrochemical capacitor. Unpassivated silicon structures, however are not stable over a long period of time due to unwanted oxidation/reduction reactions with the electrolyte, resulting in rapidly decreasing capacitance over repeated charge-discharge cycles. Our work has focused on optimizing the porous silicon nanostructure (i.e. surface area, pore morphology, etc.) and passivating the surfaces. For use as an electrochemical capacitor, surface coatings such as atomic layer deposition (ALD) titanium nitride (TiN) or carbon (e.g. graphene) [3,4] were found necessary for long-term stability. Recently published work by one of our coauthors [5] has confirmed that coating the porous silicon with graphene-like carbon can reduce these unwanted chemical reactions, greatly increasing the device’s lifetime and maximum operating voltage.

The total surface area needs to be high to obtain large capacitance, so the aspect ratio of the pores needs to be high making it difficult to coat the surfaces. Also, the high aspect ratios can lead to high effective series resistance (ESR) because of the long path that ionic charge carriers have to traverse. Two different deposition techniques were developed to stabilize the silicon surface of high aspect ratio structures: conductive coatings using ALD and thermal carbonization using gas phase treatments in a furnace [6]. Results from these structures and coatings are described.

[1] S. E. Rowlands, R. J. Latham, & W. S. Schlindwein, “Supercapacitor devices using porous silicon electrodes”, Ionics 5, 144–149 (1999).

[2] S. Desplobain, G. Gautier, J. Semai, L. Ventura and M. Roy, "Investigations on porous silicon as electrode material in electrochemical capacitors", Phys. Stat. Sol. (c), 4, 2180, 2007.

[3] D.S. Gardner, Z. Chen, W. Jin, S.B. Clendenning, E.C. Hannah, T.V. Aldridge, J.L. Gustafson, U.S. Patent Appl. 20130273261, filed Sept. 30, 2011.

[4] D. S. Gardner, W. Jin, Z. Chen, C.W. Holzwarth, C.L. Pint, B.K. Moon, and J.L. Gustafson, U.S. Patent Appl. 20140078644, filed Sept. 17, 2012.

[5] L. Oakes, A. Westover, J. W. Mares, S. Chatterjee, W. R. Erwin, R. Bardhan, S. M. Weiss, and C. L. Pint, “Surface engineered porous silicon for stable, high performance electrochemical supercapacitors”, Nature Scientific Reports, 3 , 3020, Oct. 2013.

[6] J. Salonen, M. Bjorkqvist, E. Laine, L. Niinisto, “Stabilization of porous silicon surface by thermal decomposition of acetylene”, Appl. Surface Science, 225, 389–394 (2004).