Temperature Effect on Memory Functions of the nc-CdSe Embedded ZrHfO High-k MOS Device

The nanocrystals embedded high-k  dielectric can replace the floating-gate dielectric for the  nonvolatile memory (NVM) device for advantages of low leakage current and high reliability [1]. The doped metal oxide high-k film, e.g., Zr-doped HfO₂ (ZrHfO), has good bulk and interface properties for the gate dielectric application [2]. The nanocrystalline cadmium selenide (nc-CdSe) embedded ZrHfO MOS has a large charge-trapping density with a long retention time [3]. Since in the densely packed circuit the temperature can be much higher than the room temperature, it is imperative to understand the device’s charge trapping and detrapping mechanisms at a raised temperature [4].  

                The ZrHfO/nc-CdSe/ZrHfO gate dielectric stack was sputter deposited in one pumpdown on the dilute HF cleaned p-type Si (100) wafer. The ZrHfO films were deposited from the ZrHf target in the Ar/O₂ atmosphere, i.e., 2 min for the tunnel oxide and 10 min for the control  oxide layers. The CdSe film was deposited from the CdSe target in pure Ar at 5 mTorr and 60 W for 3 min. The detailed device fabrication process can be found in ref. 3.

                Figure 1 shows J-V curves of the nc-CdSe embedded sample measured with the gate voltage V_g swept from -6 V to +6 V and then back to -6 V at 20ºC, 70ºC, and 120ºC, separately. In the negative V_g range, each curve has a peak A near V_g = 0 V, which is due to the quick release of the shallow-trapped holes. When the temperature is increased, those trapped charges are easily released because of the increase of the thermal energy  [5]. There is another peak B in the 20^ºC curve, which is  due to the Coulomb blockade effect. The size of the peak becomes negligible small at 70ºC and 120ºC because of the reduction of the Coulomb blockade effect [6].  

                Figure 2 shows the C-V curves of the nc-CdSe embedded sample measured at two different directions, i.e., from -6 V to +6 V or from +6 V to -6 V. Compared with the fresh sample measured from -2 V to +1 V, the C-V curves with V_g swept from -6 V to + 6V shifts toward the negative V_g direction because of the trap of holes from the p-type Si. The magnitude of the shift increases with the increase of the temperature because more free holes are  formed in the substrate and injected to the high-k stack [5]. On the other hand, the curve with V_g swept from +6 V to - 6V shifts to the positive V_g direction of the fresh sample because of the trap of electrons. The magnitude of the shift decreases with the increase of the temperature. According to the band diagram in ref. 3, the valence band offset is much larger than the conduction band offset between Si and HfSiO_x. At the high temperature, the electrons can be transferred through the high-k stack without being trapped to the nc-CdSe site. This is in consistent with the result of Fig. 1 where the leakage current increases with the temperature. 

                The temperature effect is also affected by the measurement frequency. For example, the C-V curves of the control and the nc-CdSe embedded samples were measured at different frequencies and temperatures. The control sample shows negligible frequency dispersion at 20^oC. But the nc-CdSe embedded sample shows the obvious frequency dispersion phenomenon. The C-V curves shifted toward the positive V_g direction when the measurement frequency was decreased from 1 MHz to 100 kHz. This is because the shallow-trapped charges, e.g., at the nc-CdSe/ZrHfO interface, respond slowly to the frequency [3]. When the temperature is increased, the amount of charges increases. More holes can tunnel back to the Si substrate at the high temperature. A should is observed in the 100 kHz curve near the flat-band voltage at 120ºC. In addition, the C-V curve slope becomes more flat with the increase of the temperature from 20ºC to 120ºC due to the increase of interface density of states.

Authors acknowledge the support of this work through the NSF CMMI 0926379 project. S. Zhang thanks Mr. Chi-Chou Lin for help in sample preparation and technical discussions.

[1] C.-H. Lin et al. JAP., 110, 024101 (2011).

[2] J. Lu et al. APL., 87, 232906 (2005).

[3] C.-C. Lin et a. JAP., 115, 084113 (2014).

[4] C. H. Yang et al. MRS Symp. Proc., 1071, F02 (2008).

[5] C.-H. Yang et al. ESL., 14, H50 (2011).

[6] C.-C. Lin et al. ECS JSSST., 2, Q16 (2013).