(Invited) Defect Generation Mechanism and Its Impact on Reliability Properties in MONOS Devices

Thursday, 9 October 2014: 14:30
Expo Center, 1st Floor, Universal 5 (Moon Palace Resort)
S. Fujii, H. Kusai, K. Sakuma, and M. Koyama (Toshiba Corporation)

Metal-oxide-nitride-oxide-semiconductor (MONOS) device attracts much attention owing to its potential as future nonvolatile memory devices. For the use of MONOS devices, it is important to understand accurately the mechanism of reliability degradation induced by electrical stress such as programming and erasing. In this paper, we discuss the defects-generation mechanisms by using evaluation technique that we developed. We also show how the defects generation influences to reliability properties of the MONOS devices.

Interface-State Generation by Program/Erase Cycling

Program/Erase (P/E) cycle stress generates defects in MONOS devices and degrades their performance and reliability. Since it has been recognized for the MONOS devices that the degradation is mainly due to interface-state generation, we examined the mechanism of interface-state generation in the MONOS devices under P/E stress by using a charge measurement technique we developed. The amount of interface states (ΔNit) is found to have a strong correlation with charges flowing during erasing, irrespective of pulse voltage, pulse width and number of P/E cycles. It is further demonstrated that the ΔNit increases as hole current dominates in erasing, suggesting that hole injection from Si substrate during erasing is the main cause for the ΔNit.

Data Retention Degradation Caused by Stress Induced Hole Current

Data retention measurements after P/E cycle stress were carried out with applying gate voltage to control the direction of electron leakage during retention. As a result, higher charge loss was observed when applying negative gate voltage during retention, indicating that P/E stress-induced leakage current (SILC) across the tunnel oxide layer degrades the data retention.

To detect the SILC directly, we performed carrier separation I-V measurement for p-channel MONOS devices. The tail of electron detrapping current at low voltage (electron SILC) was, however, observed only for the MONOS with highly Si-rich SiN charge trapping layer. Thus, a mechanism other than the electron SILC must be involved in the data retention degradation for the MONOS devices. The carrier separation measurements further demonstrated that hole current injected into the MONOS devices is increased after P/E cycle stress, indicating the existence of “hole SILC”. The hole SILC is found to be determined by the ΔNit regardless of MONOS structure, suggesting that the hole SILC is attributable to the generated interface states. These results suggest a mechanism for the data retention degradation caused by P/E cycle stress: The P/E cycle stress damages tunnel oxide layer and generates the ΔNit. The hole SILC is injected via the ΔNit, degrading data retention through hole trapping and possible subsequent recombination with stored electrons.

Impact of Interface-State Recovery on Reliability Properties

It is well known, in the research field of MOS reliability, that accumulated holes attack Si-H bonds at the Si/SiO2 interface and induce negative bias temperature instability (NBTI). Since the ΔNit in the MONOS devices is generated by holes accumulated in Si substrate, it is speculated that physical origin of the ΔNit is similar to that in MOS devices, that is, Si-H bond dissociation. The Reaction-Diffusion (R-D) model, which explains well the NBTI mechanism, suggests that hydrogen released by the Si-H dissociation diffuses back to the interface and passivates the generated interface states after removal of electrical stress. It was observed for the MONOS devices that the ΔNit was found to be decreased after 200ºC 1h baking, demonstrating that the ΔNit is due to dissociation of Si-H bonds. Since the recovery accompanies the threshold voltage shift, suppression of the ΔNit is important for data retention property as well as for endurance property.  


We have investigated the mechanisms for interface-state generation by P/E cycle stress, and demonstrated that holes injected from Si substrate is the main cause for the ΔNit. It is also found that the hole SILC is injected via the ΔNit, degrading data retention property through hole trapping and possible subsequent recombination with stored electrons. Since the physical origin of the ΔNit is Si-H bond breakage, a part of released hydrogen diffuses back to the interface and passivates the ΔNit, leading to the degradation of data retention property.