(Invited) Multilevel Cell Nonvolatile Memory with Field-effect Transistor Using Crystalline Oxide Semiconductor

Thursday, 9 October 2014: 14:00
Expo Center, 1st Floor, Universal 5 (Moon Palace Resort)
T. Matsuzaki, T. Onuki, S. Nagatsuka, H. Inoue, T. Ishizu, H. Miyairi, M. Sakakura, T. Atsumi, Y. Shionoiri, K. Kato, T. Okuda, Y. Yamamoto, J. Koyama, and S. Yamazaki (Semiconductor Energy Laboratory Co., Ltd.)
As mobile terminals become more widely used and increasingly sophisticated, the amount of data processed continues to increase. This, in turn, increases the demand for high-speed high-capacity work memory. To meet this demand, various types of nonvolatile memory, such as resistive RAM, magnetoresistive RAM, and phase-change RAM, are under development. These types of nonvolatile memory are expected to have high speed equivalent to that of DRAM and high integration equivalent to that of NAND flash memory.

A c-axis aligned crystalline oxide semiconductor (CAAC-OS) is an oxide semiconductor with crystals aligned in the c-axis direction. Use of a CAAC-OS in the active layer of an FET can provide extremely low off-state current [1]. Nonvolatile oxide semiconductor RAM (NOSRAM) using such a low off-state current has been reported [2]. A NOSRAM cell is composed of a CAAC-OS FET, a PMOS transistor, and a cell capacitor (Fig. 1). To hold charge accumulated in the capacitor of the NOSRAM cell, it is essential to prevent leakage from a node N. Such leakage is prevented by the CAAC-OS FET with ultra-low off-state current.

To reduce the size of a NOSRAM cell, the CAAC-OS FET and cell capacitor are stacked on the PMOS transistor. The main features of a NOSRAM cell are as follows:

i) An on/off ratio of approximately 107 (WLC = 0 V), which is obtained from ID-WLCcharacteristics (Fig. 2), prevents read errors due to noise.

ii) Endurance reaches 1012cycles (Fig. 3).

iii) Because the NOSRAM cell accumulates charge, a multilevel cell (MLC) is achieved by controlling the amount of charge.

iv) Controlling the amount of charge enables cell threshold voltages to be narrowly distributed at a high speed with high accuracy and without verify operations.

v) In principle, unlimited write cycles are possible because the amount of charge is controlled by the CAAC-OS FET.

However, the NOSRAM cell has more elements than other nonvolatile memory cells under development. NOSRAM already has a sufficiently high cell density, but its cell density needs to be further increased.

This paper presents an MLC achieved using a CAAC-OS FET having extremely low off-state current. One property required for an MLC is cell threshold voltage distribution. With a narrow cell threshold voltage distribution, a memory cell can have more than one level. NOSRAM cell threshold voltages are distributed with 3σ = 100 mV [2]. A test chip of a scaled-down NOSRAM has a distribution with 3σ = 55 mV and achieves an 8-level cell (3 bits/cell) (Fig. 4) [3]. To achieve an MLC NOSRAM, a CAAC-OS FET with ultra-low off-state current is required to accurately control the amount of charge at the node N. A 4-bit/cell NOSRAM can have an ideal cell size of 4 F2or less per bit, where F is the feature size. Use of the CAAC-OS technology raises expectations for the feasibility of a 16-level cell.


[1] Y. Sekine et al.: ECS Trans. 37(2011), pp. 77.

[2] H. Inoue et al.: IEEE JSSC, 47(2012) pp. 2258.

[3] S. Nagatsuka et al.: IMW, 2013, pp. 188.