(Invited) High Electron Mobility n-Channel Ge MOSFETs with Sub-Nm EOT

Monday, 6 October 2014: 14:00
Expo Center, 1st Floor, Universal 18 (Moon Palace Resort)
A. Toriumi, C. Lee, C. Lu, and T. Nishimura (The University of Tokyo, JST-CREST)
1. Introduction

The demonstration of high electron mobility in Ge n-MOSFETs is not an easy task due to unknown carrier scatterings in Ge inversion channel. The first step to clear the big hurdle is to improve the peak electron mobility by reducing the interface states density (Dit). We have succeeded in the reduction of Dit (<1011 eV-1cm-2) at Ge/GeO2 interface by employing the high-pressure O2 oxidation (HPO) [1, 2]. However, there still remain two critical challenges. One is how to suppress the significant degradation of high-Ns electron mobility (Ns: carrier density). The other one is how to keep high electron mobility in the thin EOT region [3]. Those two are of paramount importance for pushing Ge CMOS in the real technology.

2. Reinvestigation of High-Ns Electron Mobility

Coulomb scattering, phonon scattering, and surface roughness scattering are generally considered in MOS inversion layer. By employing HPO, Coulomb scattering has been dramatically reduced, resulting that the peak electron mobility in Ge n-FET is now x2.5 higher than that in Si case [1].  On the other hand, high-Nselectron mobility is generally understood from the interface roughness scattering. Here, not only the roughness height but also the roughness correlation length should be considered, according to the conventional roughness scattering theory [4, 5]. 

First, we have challenged to realize the atomically flat Ge (111) surface by using H2annealing [6] to reduce the roughness correlation length.

Next, it is discussed how the atomically flat surface is affected by the oxidation. The results show that the step and terrace structure is maintained by selecting the temperature under a high-pressure oxidation [7].

Then, excellent high-Nselectron mobility has been demonstrated.

3. EOT Reduction

Recently we have newly found two facts to breakthrough this challenge. The first one is that the low temperature HPO reduces the oxidation rate [8]. This fact enables us to achieve ~2 nm EOT GeO2 on Ge with superior interface and bulk GeO2. The other one is to replace HPO-GeO2 with high-k oxides which are thermodynamically appropriate for Ge. This means that we can use low oxygen potential oxides instead of HPO- GeO2. Then, we have reached a conclusion that Y2O3 is one of the best candidates on Ge [9]. This material is actually what we have regarded as the Ge-friendly insulator for Ge gate stacks previously from experimental viewpoint [10]. Our recent results have shown that Y2O3-doped GeO2 (YGO) is better than pure Y2O3 on Ge [11]. The resultant  electron effective mobility in Ge n-FETs at Ns=1013cm-2is significantly improved down to sub-nm EOT region.


We can engineer the Ge interface through understanding both of thermodynamics in gate stack formation and of kinetics in surface planarization and oxidation. Thus, it is concluded that Ge CMOS is quite promising.


This work was partly supported by Grant-in-Aid for Scientific Research (A) by Japan Society for the Promotion of Science (JSPS), and by the JSPS Core-to-Core Program “International Collaborative Research Center on Atomically Controlled Processing for Ultra-large Scale Integration”


[1] C. H. Lee et al., TED-58(2011)1295.

[2] K. Nagashio et al., MRS Symp. Proc. 1155(2009) C06-02.

[3] M. Caymax et al., IEDM 2009-461.

[4] Y. Matsumoto and Y. Uemura, JJAP Suppl. 2(1974) 367.

[5] C. H. Lee et al., JJAP 51(2012)104203.

[6] T. Nishimura et al., APEX 5(2012)121301.

[7] C. H. Lee et al., IEDM 2013-32.

[8] C. H. Lee et al., APEX 5 (2012)114001.

[9] C. H. Lee et al., IEDM 2013-40.

[10]A. Toriumi et al., “Advanced Gate Stacks for High-Mobility Semiconductors", pp. 257-267 (2007, Springer).

[11] C. Lu et al., APL. 104 (2014) 092909.