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(Invited) In Depth Study of Ge Impact on Advanced SiGe PMOS Transistors

Monday, 6 October 2014: 14:30
Expo Center, 1st Floor, Universal 18 (Moon Palace Resort)
A. Soussou (STMicroelectronics, CEA-LETI), M. CassÚ, G. Reimbold, C. Leroux, F. Andrieu (CEA-LETI), D. Rideau (STMicroelectronics), V. Delaye (CEA-LETI), M. Juhel (STMicroelectronics), R. Berthelon (CEA-LETI), G. Ghibaudo (IMEP-LAHC, INP Minatec), and C. Tavernier (STMicroelectronics)
SiGe material brings outstanding advantages for pMOS transistors [1,2]. Low Vt values are much easier to control thanks to specific band structure. The strain induced by engineering of lattice mismatch with silicon leads to enhanced mobility and performances. However a lot remains to understand in these processes and performances. This paper puts the light on two effects: (1) an unexpected Vt shift induced by Ge and (2) the relative impact of Ge, strain and defects on the mobility gain.

Many SiGe processes and architectures have been studied to allow clear and reproducible conclusions: (1) pMOS with a given Ge content and various stack thicknesses; (2) pMOS with a given stack and various Ge compositions; (3) SiGe pMOS performed by epitaxy or by Ge-enrichment technique, from unstrained or strained Si substrate, leading to various combinations of stress and Ge content. Both bulk and SOI devices have been processed. Data have been analyzed in a global and coherent view, thus avoiding addressing non pertinent data.

Extra Ge-induced Vfb shift:

Advanced simulations have been performed using UTOX simulator [3,4]. 6×6 kp simulations and Poisson Schrodinger allow to simulate band structures with strain effects for all %Ge as well as electrical C(V) responses. Comparison between simulations and experiments indicates an extra Vt shift which is not expected from the band structure (Fig.1). This shift is proportional to %Ge content in the channel; it has been observed on SOI and Bulk devices.

The analysis of the various gate stack thicknesses rules out an effect of charges in the stacks or at the interfaces. All the electrical data lead to a behavior explained with a Ge induced dipole at the SiGe/SiON interface. Detailed SIMS analysis (Fig.2) as well as STEM, EELS, HAADF experiments show a slight Ge diffusion in SiON probably explaining the dipole at this interface. Notice that this diffusion does not reach the SiON/HfO2 interface and the other existing dipole at this interface [5]. This result is essential for future devices design and modeling, as the extra shift is in the range of the expected Vt (~0.2V).

Mobility on strained pMOS:

The described processes induce an initial biaxial compressive stress in SiGe layer. This stress improves significantly the channel hole mobility. Meanwhile Ge atoms degrade the SiGe/SiON interface and increase the interface states density Dit (Fig.3). These Dit are related to Ge diffusion in SiON and induce dipoles. However they have no direct effect on Vt.

Using the various technological splits available we have compared splits with similar final strain but different concentrations of Ge (Fig.4). This shows that the strain generated by lattice mismatch has a 1storder effect. The percentage of Ge itself as well as generated dipoles and Dit play a minor role, at least at the low %Ge (≤30%). At higher %Ge this is no more true and the gain by strain is counter-balanced by the interface degradation. An improvement of process is required to maintain a good interface quality.

Real devices have 10-20 nm length and width. In this case the strain can relaxed depending on directions and may significantly increase or decrease the performances. A careful strain engineering is then expected. This will be discussed in the final paper.

References: [1] H. Rusty Harris et al, VLSI, p.154, 2007. [2] S. Takagi et al, IEEE TED, p.21, 2008. [3] D. Rideau et al, ULIS, p.63, 2008. [4] A. Soussou et al, Micro.Eng., 109, p.282, 2013. [5] M. Charbonnier et al., IEEE TED, p. xx, 2010.

Acknowledgment: This work was supported by the Places2be project.