ALD Grown Rare-Earth High-k Oxides on Ge: Lowering of the Interface Trap Density and EOT Scalability

The downscaling of the device dimensions in Metal Oxide Semiconductor Transistors (MOSFET) has made necessary the introduction of the high-k metal gate stack. Nowadays, silicon as channel material in MOSFET devices itself is considered as limiting factor due to a low charge carrier mobility compared to other semiconductor materials. For p-MOSFET devices Germanium is the most attractive channel material among all semiconductors as it offers holes mobility of ~1900 cm² V^-1s^-1 which is 4-times higher compared to Si. Contrary to the Si the Ge surface behaves more conflicting in contact to high-k dielectrics. Several approaches address successfully the improvement of the interface by using thin Si-layers,¹ or GeO₂ grown at high pressure,²  and by oxygen plasma.³ The Latter method leads to the lowest interface trap density (Dit) of 5x10¹⁰ eV⁻¹cm⁻²at mid-gap achieved so far.

Our approach focus on the complete removal of GeOx by thermal desorption followed by in-situ Atomic Layer Deposition (ALD) of reactive rare earth oxides like Y₂O₃ and La₂O₃. The ALD process has been carried out by using Tris(methylcyclopentadienyl)yttrium Y(MeCp)₃ for the growth of Y₂O₃, (N,N’)-diisopropylformamidinate)-lanthanum for the growth of La₂O₃, and for ZrO₂ tetrakis(dimethylamino)zirconium. As oxygen supplying agents O₂ or H₂O have been employed while temperature of the n-doped (100)-Ge substrates has been kept at 250°C during ALD.

The formation of GeO_x as well as germanates during the ALD process is proven by X-ray Photoelectron Spectroscopy (XPS). By applying well adapted annealing processes in various atmospheres Dit at mid-gap can be lowered from high values of 10¹³ eV⁻¹cm⁻² down to values close below 10¹¹ eV⁻¹cm⁻². The interfacial reaction between the high-k dielectric and the Ge surface induced by the annealing steps are characterized by XPS.

Structural and chemical investigations of the high-k oxides itself are done by performing X-ray Diffraction, XPS, and Transmission Electron Microscopy analyses. By performing Capacitance-Voltage, Current-Voltage and Conductance-Voltage measurements of MOS capacitors, a trade-off between Dit, Leakage-Current, Breakdown-Voltage on the one hand and Equivalent oxide thickness (EOT) on the other hand is observed in all cases dependent on annealing time and annealing temperature. It is also shown that the EOT can be significant lowered to values in between of 0.5 nm and 1.5 nm by using stacked oxides like Y₂O₃/ZrO₂ and La₂O₃/ZrO₂ and by applying suited layers in order to stabilize the very high-k phase of ZrO₂.

In this work, it is demonstrated that the Ge surface can be effectively passivated by using rare-earth high-k metal-oxides if suited high temperature annealing steps in oxygen and forming gas atmosphere are applied.

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