ALD Grown Rare-Earth High-k Oxides on Ge: Lowering of the Interface Trap Density and EOT Scalability

Monday, 6 October 2014: 15:00
Expo Center, 1st Floor, Universal 18 (Moon Palace Resort)
O. Bethge, C. Zimmermann, B. Lutzer, S. Simsek (Vienna University of Technology), S. Abermann (Austrian Institute of Technology), and E. Bertagnolli (Vienna University of Technology)
The downscaling of the device dimensions in Metal Oxide Semiconductor Transistors (MOSFET) has made necessary the introduction of the high-k metal gate stack. Nowadays, silicon as channel material in MOSFET devices itself is considered as limiting factor due to a low charge carrier mobility compared to other semiconductor materials. For p-MOSFET devices Germanium is the most attractive channel material among all semiconductors as it offers holes mobility of ~1900 cm2 V-1s-1 which is 4-times higher compared to Si. Contrary to the Si the Ge surface behaves more conflicting in contact to high-k dielectrics. Several approaches address successfully the improvement of the interface by using thin Si-layers,1 or GeO2 grown at high pressure,2  and by oxygen plasma.3 The Latter method leads to the lowest interface trap density (Dit) of 5x1010 eV−1cm−2at mid-gap achieved so far.

Our approach focus on the complete removal of GeOx by thermal desorption followed by in-situ Atomic Layer Deposition (ALD) of reactive rare earth oxides like Y2O3 and La2O3. The ALD process has been carried out by using Tris(methylcyclopentadienyl)yttrium Y(MeCp)3 for the growth of Y2O3, (N,N’)-diisopropylformamidinate)-lanthanum for the growth of La2O3, and for ZrO2 tetrakis(dimethylamino)zirconium. As oxygen supplying agents O2 or H2O have been employed while temperature of the n-doped (100)-Ge substrates has been kept at 250°C during ALD.

The formation of GeOx as well as germanates during the ALD process is proven by X-ray Photoelectron Spectroscopy (XPS). By applying well adapted annealing processes in various atmospheres Dit at mid-gap can be lowered from high values of 1013 eV−1cm−2 down to values close below 1011 eV−1cm−2. The interfacial reaction between the high-k dielectric and the Ge surface induced by the annealing steps are characterized by XPS.

Structural and chemical investigations of the high-k oxides itself are done by performing X-ray Diffraction, XPS, and Transmission Electron Microscopy analyses. By performing Capacitance-Voltage, Current-Voltage and Conductance-Voltage measurements of MOS capacitors, a trade-off between Dit, Leakage-Current, Breakdown-Voltage on the one hand and Equivalent oxide thickness (EOT) on the other hand is observed in all cases dependent on annealing time and annealing temperature. It is also shown that the EOT can be significant lowered to values in between of 0.5 nm and 1.5 nm by using stacked oxides like Y2O3/ZrO2 and La2O3/ZrO2 and by applying suited layers in order to stabilize the very high-k phase of ZrO2.

In this work, it is demonstrated that the Ge surface can be effectively passivated by using rare-earth high-k metal-oxides if suited high temperature annealing steps in oxygen and forming gas atmosphere are applied.

1  P. Hashemi et al. IEEE Electron Device Lett. 33 (2012), 173.
2 K. Kita et al. IEEE Electron Device Meet. (IEDM) (2009) 693.
3  R. Zhang et al. Appl. Phys. Lett, 98, (2011), 112902.
4 S. Abermann et al. Appl. Phys. Lett 94, 2629041 (2009).
5 C. Henkel et al. Solid-State Electron. 74 (2012), 7.
6 S. Abermann et al. Appl. Surf. Sci. 256 (2010), 5031.