Low Power Zinc-Oxide Based Charge Trapping Memory with Embedded Silicon Nanoparticles

Monday, 6 October 2014: 15:00
Expo Center, 1st Floor, Universal 6 (Moon Palace Resort)
A. Nayfeh (Masdar Institue of Science and Technology), A. Okyay (Bilkent University, UNAM), N. El-Atab (Masdar Institute of Science and Technology), A. Ozcan, and S. Alkis (Bilkent University, UNAM)
Recently, ZnO-based devices have attracted a growing attention because they can provide low cost, high performance, optical transparency, and high environmental stability [1-2]. In this work, the effect of embedding 2-nm Si nanoparticles (NPs) in the ZnO charge trapping layer of a ZnO-Based memory is investigated.

The channel-last memory cells were fabricated on highly doped (10-18 milliohm-cm) p-type (111) Si wafer. First a 15-nm-thick Al2O3 blocking oxide is first deposited by ALD using a Savannah 100 system, followed by a 2-nm-thick ZnO charge trapping layer. Then, Si-NPs were spun on the ZnO. Again, a 2-nm-thick ZnO charge trapping layer followed by a 3.6-nm-thick Al2O3 tunneling oxide and an 11-nm-thick ZnO channel were ALD deposited at 250°C. The source and drain contacts were created by depositing 100 nm Al by thermal evaporation followed by lift off. Rapid Thermal Annealing in forming gas (H2:N2 5:95) was performed on the samples for 10 min at 400ºC.

            The memory cells were probed using the Agilent-Signatone probe station. In order to program and erase the memory cell -10V/10V is applied on the gate for 5 sec with the source and drain being grounded. In order to read the state of the cell, the gate voltage is swept from 0V up to 20V with a drain voltage Vd of 10 V with the source being grounded. The memory cells were being programmed by applying a negative gate voltage and erased by applying a positive gate voltage, indicating that holes are being trapped. The measured Idrain-Vgate curves of the programmed and erased states of memory devices with and without Si NPs are plotted in Fig. 1 showing a higher threshold voltage shift (ΔVt) with the Si NPs. This shows that the Si NPs behave as charge trapping centers with a high trapping density within the bandgap of ZnO. Also, the samples were programmed and erased at different voltages. It was observed that at a very low program/erase voltage of -1V/1V, the Vt shift can be as high as 3.4 V due to the Si-NPs, which suggests that holes emission is done via a low electric field mechanism.

In order to determine the mechanism of holes emission, ΔVt versus the square root of the electric field across the tunnel oxide is plotted. The linear trend  indicates that Poole-Frenkel is the dominant mechanism of emission of holes at an low electric field E = 0.36 MV/cm which corresponds to Vg = 1 V. In fact, due to Poole-Frenkel Effect, the barrier height for the holes (ΔEv = 1.36 eV) is further lowered in the presence of an electric field by a calculated amount of 0.16 eV at Vg = 1 V which exponentially increases the holes emission rate [1].

 In summary, the large ΔVt obtained with Si NPs at low voltages highlight a promising technology for future low power and low cost memory devices.   

 Acknowledgment: This work was supported by ATIC, and TUBITAK Grants 109E044, 112M004, 112E052 and 113M815.


[1]    Nazek El-Atab, Ayse Ozcan, Sabri Alkis, Ali K. Okyay, and Ammar Nayfeh "Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission", Appl. Phys. Lett. 104, 013112 (2014).

[2] Nazek El-Atab, Ayman Rizk, Ali K. Okyay, Ammar Nayfeh, “Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer” AIP advances 3, 112116 (2013