Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Monday, 6 October 2014: 13:00
Expo Center, 1st Floor, Universal 4 (Moon Palace Resort)
M. Yamano, S. I. Kuroki, T. Hirata, T. Sato (Research Institute for Nanodevice and Bio Systems (RNBS)), K. Kotani (Graduate School of Engineering, Tohoku University), and T. Kikkawa (Research Institute for Nanodevice and Bio Systems (RNBS))
Highly biaxially oriented linearly arranged poly-Si thin films were formed by double line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and energetically stable Σ3 grains boundary were observed dominantly. Silicon grains were elongated in the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were fabricated. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low temperature (≦550 o C) by a metal gate self-aligned process.

The TFTs were fabricated as follows. A-Si of 150 nm thickness and cap SiO2 of 100 nm thickness were deposited on a quartz substrate. CW laser crystallization with double-line spot irradiation (wavelength: 532 nm, laser power: 8.5 W, scan speed: 0.25 cm/s) on a-Si was carried out, and lateral-crystallized poly-Si was formed. After the laser crystallization, the cap SiO2 was etched using buffered HF aqueous solution (BHF), and lithography and dry etching (Cl2: 40 sccm, HBr: 40 sccm) were performed in order to pattern the poly-Si active layer. Next, gate SiO2 of 50 nm thickness was deposited by inductively coupled plasma chemical vapor deposition (ICP CVD, SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and a Mo gate electrode of 200 nm thickness was deposited by sputtering method. After lithography patterning, wet etching of Mo was carried out with a solution of H3PO4: HNO3: CH3COOH: H2O= 400: 25: 50: 25 and the gate electrode was formed. A self–aligned source and drain system was formed by As ion doping (ion dose: 2×1015 cm-2, acceleration voltage: 66 keV) using the Mo gate electrode as the mask. Activation annealing treatment was carried out at 550o C in N2 ambient for 30 min. A sacrificial oxide layer in the S/D region was removed using BHF. After the removal, 150-nm-thick interlayer insulation films were deposited by atmospheric pressure chemical vapor deposition (APCVD), and the contact hole was etched using BHF. A Mo metal pad was deposited by sputtering method, and finally sintering processing was carried out at 400 o C in H2ambient for 30 min. Figure 1 shows a microphotograph of the fabricated DLB-CLC poly-Si TFT.

A TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. At the electron field effect mobility, its variation was within 10% at same crystallization region. High-performance TFTs with DLB-CLC were demonstrated, however it was found that off-leakage current was relatively large. The leakage current mechanism was investigated by measuring temperature dependence of the TFT characteristics. The field-effect mobilities at the ON region were proportional to T-1.5 as shown in Fig. 2. The result shows the phonon scattering was dominant as same as single silicon crystal. On the other hand, in the OFF region, the electrical conductivity shows logarithmic behavior as a function of exp{-EB/kBT} as shown in Fig. 3. This leakage current shows that there are many trap states in the grain boundaries.