Improved Bilayer Graphene Transistors for Applications in Nanoelectronics

Introduction

In this contribution we report on an improved method to fabricate transfer-free bilayer graphene transistors (BiLGFETs) directly on oxidized silicon wafers in a silicon-CMOS compatible fabrication process. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1x10⁵ and 1x10⁷ at room temperature [1] exceeding previously reported values by several orders of magnitude. However, at this stage, the maximal on-state current of a BiLGFET is limited by the contact resistance, since the catalyst areas are simultaneously used as source (S) and drain (D) contacts. In order to improve device performance, an additional fabrication step has been developed, by which means the contact resistance is lowered by more than a factor of 10.

 Results and Discussion

In preparation for CCVD silicon wafers are oxidized in dry O₂ ambient to obtain a 100nm thick SiO₂ film. Afterwards a first lithography step follows and a structured liftoff system remains on the wafer surface. Thin aluminum and nickel layers are evaporated over the whole substrate surface and are structured via liftoff. By annealing the wafer the aluminum transforms itself into insulating aluminum-oxide (Al_xO_y) while the nickel layer generates several nickel nanoclusters at the perimeter of the catalyst system [2]. In the subsequent methane-based CCVD process, graphene layers are growing (Fig. 1). The number of the stacked graphene layers (i.e. mono-, bi- or few-layers) depends on the adjusted process parameters like time, temperature and gas mixture [2]. Raman-measurements (Fig. 2) and AFM-step height measurements (not shown here) have been performed to confirm the presence of bilayer graphene. In order to improve S/D contacts, one additional lithography step is performed subsequent to the CCVD growth process (Fig. 3). The second mask-layer is used to cover the central part of the graphene channel (channel length is about 3µm) while the edges (>0.2µm) at the catalyst/graphene transition and the S/D regions are unexposed (Fig. 3(b)). Following the lithography step, a 70nm thick palladium layer is evaporated over the whole wafer surface. Due to the high aspect ratio of the resist, the S/D contacts are electrically separated. The contact metal palladium is in direct contact with the graphene channel to improve conduction.

The electrical characterization of the graphene devices has been performed using a Keithley SCS 4200 semiconductor parameter analyzer. Electrical results indicate that the current drive for BiLGFETs with Pd-enforced S/D contacts is improved by approximately one order of magnitude. However, post-processing after graphene-growth affects the over-all current-voltage characteristics e.g. in terms of threshold-voltage shift. Further details will be presented and discussed at the meeting.

References

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3. A.C. Ferrari, J.C. Meyer, V. Scardaci, C. Casiraghi, M. Lazzeri, F. Mauri Phys. Rev. Lett. 97, 187401 (2006)