Invited: Scaling Mosfets with Self-Aligned Super-Steep-Retrograde-Well

Tuesday, 7 October 2014: 13:30
Expo Center, 1st Floor, Universal 7 (Moon Palace Resort)
H. Zhu (Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences)
With aggressively reducing of MOSFET area or IC manufacturing costs, the design space to satisfy both device performance and power consumption requirements becomes very limited. Although strain engineering and high-k/metal gate (HKMG) technique were successfully used to scale planar bulk device down to 28nm technology node, further reduction of gate length requires use of fully depleted channel (FDC) to control short channel effect (SCE). FinFET [1] and UTBB SOI [2] are two typical device structures using FDC. However, significant structural and process changes are involved for both FinFET and UTBB SOI implementations. Super steep retrograde well (SSRW) [3] can be used to reduce depleted depth in the channel of bulk MOSFETs with minor process changes. Two major drawbacks for the devices with SSRW are 1) large band-to-band tunneling (BTBT) or leakage between SSRW and source/drain/extension caused by high doping level and 2) difficult to keep abruptness of SSRW due to large thermal budget used in fabrication process, especially source/drain annealing. To fully take the advantage of state-of-the-art integration flow of all gate last HKMG [4], we propose a new method, called self-aligned SSRW, which forms a SSRW self-aligned to the gate of a bulk MOSFET in replacement gate process. The formation of self-aligned SSRWs can avoid source/drain annealing step and reduce the overlap between SSRW and source/drain/extension. A steep retrograde well can be achieved by a relatively low temperature spike annealing or laser annealing.

Self-aligned SSRW CMOS devices have been fabricated on 200mm Si wafers in our lab. In this paper, we will review and report the first self-aligned SSRW nMOSFETs and pMOSFETs with all-last HKMG process. To investigate the SCE control and BTBT effect by SSRW, an asymmetrical device structure, replaced metal spacer gate (RMSG) MOSFET with an asymmetrical SSRW doping is also introduced. The MOSFETs with self-aligned SSRWs show good SCE control and low off current at a gate length of 25 nm. Dramatically improved DIBL and Ion/Ioff characteristics have been achieved when SSRW doping is used to replace the conventional halo doping. It turns out that with self-aligned SSRW drain-to-body leakage is reduced by upto two decades due to reduction of BTBT leakage current between channel and SD/extension. We have demonstrated that the self-aligned SSRW process is simple and fully compatible with state-of-the-art all gate last CMOS technology, promising for device performance improvement and mass production towards scaling of MOSFETs. Simulations and further improvements for bulk and SOI MOSFETs with self-aligned SSRWs are also discussed.

[1] C. H. Jan et al., IEDM Tech. Dig., pp. 44-47 (2012)

[2] L. Grenouillet et al., IEDM Tech. Dig., pp. 64-67 (2012).

[3] Z. Ren et al., IEDM Tech. Dig., pp. 733 – 736 (2005).

[4] P. Packan et al., IEDM Tech. Dig., pp. 2841-2844 (2009)