The Role of Passivation Layer during Thermal  Annealing for Oxide Semiconductor Thin Films

Tuesday, 7 October 2014: 14:00
Expo Center, 1st Floor, Universal 4 (Moon Palace Resort)
C. S. Hwang (ETRI), S. H. K. Park (KAIST), S. H. Cho, M. K. Ryu, H. Oh, S. J. Lee, J. H. Yang, C. Byun, J. Park, K. I. Cho (ETRI), and H. Y. Chu (Electronics and Telecommunications Research Institute (ETRI))
Oxide TFTs have been considered as a good candidate for the application to backplane device for  high quality TFT-LCD and large area OLED panel. It is well known that the passivation play the very important role for the development of the high quality oxide TFTs. The criteria for good passivation layer can be a barrier for environmental factors, not having doping source during thermal annealing, and playing a role of curing the defective interface.

The evolution of the resistance of active films during thermal annealing was monitored under the split of passivation layers and active layers. ALD deposited Al2O3 layer and PECVD SiO2 layer were applied for the passivation layer and sputter deposited Al-doped InZnSnO and InGaZnO were applied for the active layer.

It is found that Al2O3 passivation layer supplies dopants to the active interface (possibly H) during high temperature annealing and the side wall of AIZTO pattern contains many defects, which become dopants during high temperature annealing through detailed measurement of resistance of patterned oxide thin films with various sizes.

It is suggested that PECVD SiO2 with proper pre-treatment (possibly N2O plasma treatment) will be best candidate for the passivation layer in the oxide TFTs, especially in the case of oxide TFTs with high mobility.