(Invited) Gate Insulator for High Mobility Oxide TFT

Tuesday, 7 October 2014: 09:00
Expo Center, 1st Floor, Universal 4 (Moon Palace Resort)
S. H. K. Park (KAIST), H. O. Kim, S. H. Cho, M. K. Ryu, J. H. Yang (ETRI), J. B. Ko (KAIST), and C. S. Hwang (ETRI)
High resolution display are considered to need oxide TFTs with higher mobility than 30 cm2/V.s and less parasitic capacitance. Until recently, many active materials for high mobility TFT such as ZITO1, AZITO2, IGO3, In rich IGZO4, and ZnON 5 have been reported. The proper device structure with less parasitic capacitance is known to be self-aligned top gate TFT. In designing high performance high mobility oxide TFT gate insulator deposition is very critical process especially in top gate TFT due to the difficulty in controlling the carrier amounts of high mobility oxide semiconductor. PECVD process of SiO2 induces not only H incorporation into the below layer but result in SiO2 with large amounts of H. O-H in dielectric layer is thought to be the origin of hole trapping site. Besides it causes negative Vth shift after annealing of TFT. Therefore it is very important to deposit SiO2gate dielectric film with less H without inducing H incorporation into the active layer.

As the preliminary structure of top gate self-aligned TFT, we fabricate top gate staggered TFT with ITO as SD electrode, IGZO as active layer, SiO2 grown by PEALD at 250oC as the first gate insulator, SiO2 deposited by PECVD at 350oC as the main gate insulator, and Mo as the gate electrode.

While the TFT annealed at 250oC showed the mobility, Vth, and S.S to be 35.5 cm2/V.s, 0V, and 0.27 V/dec., respectively, those annealed at 300oC were 39.9 cm2/V.s, -1V, and 0.32 V/dec., respectively. The annealing TFT at higher temperature than the deposition temperature of first gate insulator induced negative Vth shift from 0V to -1V with increase of mobility. A noteworthy is the stability behavior under positive/temperature stress. IGZO TFT annealed at 250oC showed positive Vth shift of 3.28V under 20V at 60oC for 10K seconds. Meanwhile that annealed at 300oC was shifted by 0.28V after same condition without change of S.S value.

Positive shift of Vth under positive bias stress was mostly blamed on the defect generation at the interface and it can be alleviated by thermal annealing. However, we could not identify the origin of defects and curing mechanism by thermal annealing. After several investigations on the interface defects and annealing process, we suggest that the main origins of bias instability are oxygen interstitial as well as the weak bond formation at the interface from the plasma process during GI or active deposition. In addition, these defects can be cured by H passivation which can be incorporated during the annealing process. Therefore H in the adjacent film of active layer can be not only a bad player in terms of carrier generation but good player in a view point of passivation of defects in active layer and interface of oxide TFT.


[1] M. K. Ryu, S. Yang, S.-H. K. Park, C.-S. Hwang, and J. K. Jeong, IEEE Electron Device Letters, 31 (2), 144 (2010)

[2] S. Yang, D. H. Cho, M. K. Ryu, S. H. Ko Park, C. S. Hwang, J. Jang, and J. K. Jeong, IEEE Electron Dev. Lett. 31, 144 (2010)

[3] K. Ebata, S. Tomai, Y. Tsuruma, T. Iitsuka, S. Matsuzaki, and K. Yano, Applied Physics Express 5, 011102 (2012)

[4] T. Arai and T. Sasaoka, SID Int. Symp. Digest Tech. Papers, 710 (2011).

[5] Y. Ye, R. Lim, and J. M. White, JOURNAL OF APPLIED PHYSICS 106, 074512 (2009)