(Invited) High Performance III-V-on-Insulator MOSFETs on Si Realized by Direct Wafer Bonding Applicable to Large Wafer Size
In this novel DWB technique using a Si donor wafer, InGaAs/InxAl1-xAs/GaAs layers were epitaxially grown on Si substrates first. After Al2O3 atomic layer deposition as a BOX layer, CMP has been carried out for surface smoothing for Al2O3/III-V/Si wafer and wafers were bonded each other. Subsequent wet etching thinned the top Si and the III-V buffer layers, resulting in the formation of InGaAs-OI on Si substrates. While the present demonstration has employed 4-inch Si host substrates, this technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost.
The high film quality has been confirmed by Raman and photoluminescence spectra. Also, in order to evaluate the electrical properties, InGaAs-OI MOSFETs was fabricated with the same fabrication process as in the present works [5-8]. Here, gate stack was composed of 10 nm Al2O3 and Ta gate metal. S/D was formed by Ni-InGaAs metal S/D. We have confirmed the good ID-VG curves with a subthreshold slope of 100 mV/dec and on/off ratio > 106 for InGaAs-OI MOSFETs with body thickness of 9 nm and LG of 1 μm.
The high electron mobility of 1700 cm2/Vs and the mobility enhancement of 3× against Si MOSFETs have been demonstrated. InGaAs-OI MOSFETs fabricated from the Si donor wafer exhibit high mobility comparable to that from the InP donor wafer, indicating that the present wafer fabrication process can realize sufficiently high quality InGaAs-OI on Si wafers with the same level as those obtained from the InP donor wafer. The leakage current of InGaAs-OI MOSFETs fabricated from the Si donor wafer is also found to be uniform and as low as that from the InP donor wafer. As a result, thanks to the change of donor wafers from InP to Si, the present integration scheme of DWB for InGaAs-OI provides excellent wafer scalability up to the Si wafer size > 300 mm with maintaining high device quality.
This work was partly supported by the Innovation Research Project on Nano electronics Materials and Structures, and Research and Development Program for Innovative Energy Efficiency Technology from NEDO and JST-CREST. The authors would like to thank Drs. M. Hata, T. Osada, O. Ichikawa, and H. Yamada in Sumitomo Chemical Corporation for their collaborations.
References  S. Takagi et al., Solid-State Electron. 51, 526 (2007)  S. Takagi et al., IEEE Trans. Electron Device 55, 21 (2008)  M. Yokoyama et al., IEEE Electron Device Lett. 32, 1218 (2011)  M. Yokoyama et al., Appl. Phys. Exp. 2, 124501 (2009)  S.-H. Kim et al., Appl. Phys. Exp. 5, 014201 (2012)  S.-H. Kim et al., IEEE Trans. Nanotechnol. 12, 621 (2013)  S.-H. Kim et al., IEEE Trans. Electron Devices 60, 2512 (2013)  S.-H. Kim et al., Appl. Phys. Lett. 104, 263507 (2014)  M. Yokoyama et al., SSDM, 206 (2013)  M. Yokoyama et al., VLSI symp., 28 (2014)