(Invited) High Performance III-V-on-Insulator MOSFETs on Si Realized by Direct Wafer Bonding Applicable to Large Wafer Size

MOSFETs using III-V channels with high mobility and low effective mass have been regarded as strongly important for obtaining CMOS under sub 10 nm technology nodes [1, 2]. One of the critical issues to realize III-V MOSFEs is to form high quality III-V films on large size Si wafers. This heterogeneous integration of III-V devices on Si wafers must be explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. The existing methodologies could have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. We have already proposed and demonstrated ultrathin-body (UTB) InGaAs- and GaSb-based channel formation on Si substrates by using direct wafer bonding [3-10]. A UTB (3.2 nm InGaAs)/ultrathin buried oxide (UTBOX) (Al₂O₃(4.4 nm)/SiO₂ (3.3 nm))/Si substrate [3] and a UTB quantum well channel (3 nm InGaAs/3 nm InAs/3 nm InGaAs/ UTBOX/Si) substrate [7, 8] have provide superior MOSFET performance due to the high channel material quality. Here, the III-V channels epitaxially-grown on III-V substrates have been transferred to Si substrates, indicating that the wafer size of III-V layers is limited to that of the available III-V host substrates such as InP. As a consequence, this method is not simply applicable to III-V-on-Si substrates with large Si wafer sizes of 300 nm and beyond. In this study, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on an InP donor wafer.

In this novel DWB technique using a Si donor wafer, InGaAs/In_xAl_1-xAs/GaAs layers were epitaxially grown on Si substrates first. After Al₂O₃ atomic layer deposition as a BOX layer, CMP has been carried out for surface smoothing for Al₂O₃/III-V/Si wafer and wafers were bonded each other. Subsequent wet etching thinned the top Si and the III-V buffer layers, resulting in the formation of InGaAs-OI on Si substrates. While the present demonstration has employed 4-inch Si host substrates, this technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost.

The high film quality has been confirmed by Raman and photoluminescence spectra. Also, in order to evaluate the electrical properties, InGaAs-OI MOSFETs was fabricated with the same fabrication process as in the present works [5-8]. Here, gate stack was composed of 10 nm Al₂O₃ and Ta gate metal. S/D was formed by Ni-InGaAs metal S/D. We have confirmed the good I_D-V_G curves with a subthreshold slope of 100 mV/dec and on/off ratio > 10⁶ for InGaAs-OI MOSFETs with body thickness of 9 nm and L_G of 1 μm.

The high electron mobility of 1700 cm²/Vs and the mobility enhancement of 3× against Si MOSFETs have been demonstrated. InGaAs-OI MOSFETs fabricated from the Si donor wafer exhibit high mobility comparable to that from the InP donor wafer, indicating that the present wafer fabrication process can realize sufficiently high quality InGaAs-OI on Si wafers with the same level as those obtained from the InP donor wafer. The leakage current of InGaAs-OI MOSFETs fabricated from the Si donor wafer is also found to be uniform and as low as that from the InP donor wafer. As a result, thanks to the change of donor wafers from InP to Si, the present integration scheme of DWB for InGaAs-OI provides excellent wafer scalability up to the Si wafer size > 300 mm with maintaining high device quality.

This work was partly supported by the Innovation Research Project on Nano electronics Materials and Structures, and Research and Development Program for Innovative Energy Efficiency Technology from NEDO and JST-CREST. The authors would like to thank Drs. M. Hata, T. Osada, O. Ichikawa, and H. Yamada in Sumitomo Chemical Corporation for their collaborations.

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