(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

Tuesday, 26 May 2015: 11:30
Williford Room B (Hilton Chicago)
O. Weber (CEA-LETI), E. Josse, and M. Haond (STMicroelectronics)
As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5].

Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated.

After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node.

As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd.

These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.


[1] C.-H. Jan et al., IEDM Tech. Dig., 2012,

[2] S.-Y. Wu et al., IEDM Tech. Dig., 2013,

[3] N. Planes et al., VLSI Symposium Tech. Dig., 2012,

[4] F. Arnaud et al., IEDM Tech. Dig., 2012,

[5] O. Weber et al., VLSI Symposium Tech. Dig., 2014,

[6] D. Golanski et al., VLSI Symposium Tech. Dig., 2013,

[7] K. Cheng et al., IEDM Tech. Dig., 2012.