(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS
Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain . Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built . The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges  (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated.
After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node.
As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in  a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd.
These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.
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