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Germanium Junctionless MOSFET with Steep Subthreshold Swing
Apart from the potential for low power logic, analog and RF applications, JL MOSFETs exhibit steeper Subthreshold Swing (S-swing) due to impact ionization phenomena at relatively lower drain voltages in comparison to conventional inversion mode transistors [3]. The steep S-swing for symmetric gate operation in silicon Double Gate (JL) was obtained at a drain bias (Vds) of 2 V. A possible option to reduce the Vdsrequired to trigger impact ionization is to use a lower bandgap material such as Germanium (Ge), which is also considered as strong candidate for future devices due to higher carrier mobility.
In this work, Ge JL Double Gate (DG) n-channel MOSFETs (figure 1) have been studied using ATLAS simulation tool [4]. Our simulation results, published earlier [5-6], for silicon JL MOSFETs depicting steep S-swing, hysteresis, increase in the number of decades of drain current transition with applied drain bias are in good qualitative agreement with the experimental results on silicon JL transistors [3]. In this work, we focus on Ge JL transistors and analyze the impact of impact ionization for achieving steep S-swing values at low drain bias. Our results (figure 2) show an impact ionization triggered steep transition in the subthreshold current with an ideal S-swing (< 1 mV/decade) at a drain bias of 1.3V. The phenomenon of impact ionization in Ge JL MOSFETs is analyzed in terms of Generation-Recombination (G-R) rates and the product of current density and electric field (J.E). Results show that a current transition of nearly 3.5 is achieve in Ge JL MOSFETs at the onset of steep S-swing while the same is limited an order in Si JL transistors. Ge based devices also exhibit a higher value of (J.E) which is directly correlated with the higher degree of impact ionization in the device. The work demonstrates new opportunities for achieving steep subthreshold swing at relatively lower drain voltages in emerging technologies.
Acknowledgement:
This work is supported in part by University Grants Commission, Government of India, through the Junior Research Fellowship (JRF) award to Manish Gupta (Ref.: 4015/NET-June2013), and in part by the Science and Engineering Research Board, Department of Science and Technology, Government of India, under Grant SR/S3/EECS/0130/2011.
References:
[1] International Technology Roadmap for Semiconductors (www.itrs.net)
[2] J.-P. Colinge et al.,Nature Nanotechnology, 5, pp. 225-229, 2010.
[3] C.-W. Lee et al.,Applied Physics Letters, 96, 102106, 2010.
[4] ATLAS Users Manual
[5] M.S. Parihar et al., Applied Physics Letters, 101, 093507, 2012.
[6] M.S. Parihar et al., Applied Physics Letters, 101, 263503, 2012.