Using the Wave Layout Style to Boost the Digital ICs Electrical Performance in the Radioactive Environment

Tuesday, 26 May 2015: 14:50
Williford Room B (Hilton Chicago)
R. Navarenho de Souza, M. Guazzeli da Silveira, and S. P. Gimenez (University Center of FEI)
This paper presents an experimental comparative between the Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET) manufactured with the Wave (S gate geometry) and the standard layout (CnM) considering the Total Ionizing Dose (TID) effects. Due to the special characteristics of the bird’s beaks regions of the Wave MOSFET (WnM), this innovative layout proposal for MOSFETs is able to improve the device TID tolerance without add cost to the Complementary MOS (CMOS) manufacturing process.


The TID effects cause long term damage in the oxide layers of the electronic devices, worsening the electrical performance of the MOSFET [1]. New materials, multiple-gates and three-dimensional (3D) devices are under intense research and development [1], as seen in the International Technology Roadmap for Semiconductor (ITRS) [2], in order to overcome the scaling limits [3-5]. Several efforts have been made to improve the devices radiation hardness, which mainly can be divided in two categories: one is related to the optimization of CMOS manufacturing process with different materials and technologies and the other focus on using non-standard layout for MOSFET. In this context, the innovative Wave nMOSFET [6] can be an alternative to boost the TID tolerance. Therefore, the purpose of this paper is to present an experimental comparative study of the TID effects between the WnM and CnM,  considering the main digital parameters (on-state drain current, ION, off-state drain current, IOFF and the ION/IOFF ratio.


Figure 1 presents the layout of the WnM. It is possible to observe the gate, the drain and source for the superior and inferior semicircles, the longitudinal electrical field  in the channel, and the bird's beak regions (BBR). 

Observe that the WnM superior semicircle is in internal drain bias configuration (IDBC), while the inferior semicircle is in external drain bias configuration (EDBC), then the longitudinal electric field (LEF) in those semicircles are different, thus it affects the electrical behavior of the parasitic transistors associated to the WnM BBRs, and as a result, the TID effects are different.


The WnM and the CnM were exposed to 10 keV X-rays irradiation using a Shimadzu XRD-7000 for  cumulative dose of 1.5 Mrad (first dose of 1 Mrad and second dose of 500 krad) at a dose rate of 400 rad/s in biased devices. The “ON” bias was applied, where the gate is at the bias supply voltage (5 V), and the source, drain, and substrate are grounded (0 V). The devices were manufactured by using the 0.35 μm ON Semiconductor conventional (Bulk) manufacturing CMOS process, via MOSIS Educational Program (MEP) [7].


Figure 2 illustrates the experimental curves of the WnM and the CnM counterpart (channel length, L, of 2.3 mm) of the logarithm of the drain current normalized [IDS/(W/L)] as a function of the overdrive gate voltage [VGT], for a drain bias (VDS) of 4 V.

By analyzing the Fig. 2, the WnM ION is 9.5% higher than the CnM and the IOFF of both devices are similar in pre-radiation.  However, after TID of 1.5 Mrad, the CnM IOFF is about 10% higher than the one found in the WnM counterpart. Furthermore, the WnM ION/IOFF ratio is about 30% higher that found in the equivalent CnM. This is because of the different BBR influence of the WnM compared to the CnM counterpart. IDBC has a smaller drain area and higher LEF, the EDBC is the opposite, as a result, the TID effects are different and they affect the digital electrical parameters.  


The Wave layout style to be implemented in MOSFETs is an alternative to boost the TID tolerance and digital ICs operating in radioactive environment (space and medical applications), due to its special layout and different BBR characteristic.


[1] H. Barnaby, “Total-Ionizing-Dose effects in modern CMOS technologies,”  IEEE Trans. Nuc. Sci., vol. 53, no. 6, pp. 3103- 3120, 2006.

[2] International Technology Roadmap for Semiconductors.

[3] G. K. Celler and S. Cristoloveanu, “Frontiers of silicon on insulator,” J. Appl. Phys., vol. 93, no. 3, pp. 4955, 2003.

[4] J.P. Colinge, et  al, “Silicon on insulator “gate all around” device,” in Proc. IEDM Tech. Dig., pp. 595, 1990.

[5] M. Vinet, et al, “Bonded planar double-metal-gate NMOS transistors down to 10 nm,” IEEE Elec. Devic. Lett., vol. 26, no. 5, pp. 317, 2005.

[6] S. Gimenez,  “The Wave SOI MOSFET: A New Accuracy Transistor Layout to Improve Drain Current and Reduce Die Area for Current Drivers Applications,” ECS Trans., v. 19. pp. 153-158,  San Francisco, 2009.

[7] MOSIS Service, 2010.