N-Junctionless Transistor Prototype: Manufacturing Using a Focused Ion Beam System

Tuesday, 26 May 2015: 14:30
Williford Room B (Hilton Chicago)
L. P. B. Lima (School of Electrical Engineering, University of Campinas, Chemistry Department, KULeuven), M. V. P. dos Santos, M. A. Keiler (School of Electrical Engineering, University of Campinas), H. F. W. Dekkers (Imec), S. De Gendt (imec vzw), and J. A. Diniz (School of Electrical Engineering, University of Campinas, Center for Semiconductor Components, Unicamp)
Junctionless (JL) devices have been widely studied due to their compatibility with CMOS technology and can be useful concepts for 3D devices. Also, these devices demonstrate low leakage current, good sub threshold slope, and, at high temperature, present high mobility and little diffusion of impurities. Electron beam lithography, UV lithography, reactive ion etching (RIE) and inductively coupled plasma (ICP) have been used for JL device fabrication. In addition, recently focused ion beam (FIB) system has been used for sample preparation in transmission electron microscopy (TEM) and for micro and nanofabrication as application in circuit editing and prototype nanomachining. One advantage of using FIB system is that it does not require lithography for milling (for example, Si milling) and has nanometer resolution. Although, some surface damage or ion incorporation on the substrate surface can occur due to Ga+ FIB, which leads to changes of the substrate optical and electrical properties. However, this effect is desirable in some cases and FIB system can also be used for ion implantation. In addition, FIB system can deposit metallic and dielectric layers, such as platinum (Pt) and silicon dioxide (SiO2), respectively. In this context, nMOS (metal-oxide-semiconductor) JL devices were fabricated on silicon-on-insulator (SOI) substrates using  Ga+ FIB system for silicon milling, to get the gate dielectric (SiO2) and the gate, drain and source electrodes (Pt), respectively. Width, length and height dimensions of Si nanowire were 80 nm, 4 µm and 80 nm, respectively. Energy dispersive spectroscopy (EDS) measurements were taken to study the surface compositions of Si NW, dielectric and electrodes. Those analyses confirm the SiO2 and Pt deposition by Ga+ FIB. Also, Ga+ incorporation on Si nanowire surface were also observed by EDS measurements. To evaluate the Ga+ incorporation influence on JL devices, two different transistor sets were fabricated: the JLFIB (Figure 1a), fabricated entirely by FIB system, and JLRFIB (Figure 1b), fabricated using RIE (to Si etching and MESA definition) and FIB. With this, JLRFIB presents lower Ga+ incorporation than JLFIB device. Additionally, the effect of Ga+ incorporation on Si was also investigated by TCAD SILVACO simulations of 3D JL devices with the same dimensions of the fabricated JL devices (Figure 2). Id x Vds measurements of JLFIB and JLRFIB devices were carried out (Figure 3) and indicate that these devices are working like a gated resistor or JL device. The distortions on Ids x Vds curves can be attributed to Ga+ incorporation, which increases the SiNW net doping and creates some dopant gradient between the SiNW and the source/drain regions (like a p-n junction) conducting to a non-linear behavior in Ids x Vds curves.  Moreover, the C concentration (from the organometallic) in the Pt sorce/drain electrodes deposited by Ga+ FIB decreases the electrodes workfunction and results in a Schottky-like electrical contact in source/drain regions, either leading to non-linear curves. A solution for this non-ohmic behavior is achieved by replacing the source/drain electrodes by PVD Al contacts. Furthermore, the extracted values, from Ids x Vgs curves (Figure 3c), for slope are lower than 100 mV/decade, which approach the ideal value of 60 mV/decade. Finally, those results indicate that our fabrication method using FIB system can be used to obtain prototypes of JL devices on a lab scale.