(Invited) Advanced Semiconductor Devices for Future CMOS Technologies
Beside changing the gate concept such as in FinFETs, devices with an operation mechanism different from thermionic emission are explored. Tunnel Field Effect Transistors (TFETs) are based on band-to-band-tunneling and allow to achieve subthreshold swings below 60 mV/dec, thereby reducing the power consumption (2). Both horizontal and vertical TFET approaches are emerging as post-CMOS alternatives with a strong potential for future technologies. Further scaling leads to gate-all-around (GAA) and nanowire devices.
The quest for higher drive currents triggers beside stress engineering the use of mobility boosters associated with high mobility materials like Ge and III-V. The strong progress made in epitaxial growth techniques resulted in the fabrication of Ge (optimal for p-channel performance), III-V (optimal for n-channel devices) or hybrid Ge/III-V devices on a Si substrate (3). Very good performance has been demonstrated at device level. These high mobility materials are also implemented in TFET and nanowire structures.
Near the end of the roadmap the research efforts are focused towards carbon-based materials like carbon nanotubes (4) and graphene (5), spintronics (6), magnetic tunnel junctions and the use of 2D materials such as transition metal dichalcogenides (MX2) like MoS2 and NbSe2(7). For several of these approaches device feasibility has already been demonstrated.
This paper analyzes the status and the challenges of several of these advanced CMOS technologies (some of them are illustrated in Fig. 1) and outlines potential limitations for future scaling in view of important electrical parameters such as variability, noise performance and reliability. A technology benchmarking will be given.
1) Q. Liu et al., Techn. Digest IEDM, 228 (2013).
2) A. Ionescu and H. Riel, Nature, 479, pp. 329 (2011).
3) S. Takagi and M. Takenaka, Proc.10thInt,. Conf on Solid-State and Integrated Circuit Technology (ICSICT), 53 (2010).
4) H.-S.P. Wong and D. Akinwande, Carbon nanotubes and graphene device physics, Cambridge University Press, 2011.
5) V. Skakalova and A.B. Kasier, Graphene: Properties, preparation, characterization and devices, Woodhead Publ., Elsevier, 2014.
6) S. Sugahara and J. Nitta, Proc. IEEE, vol. 98, 2124 (2010).
7) F. Schwierz and J. Pezold, Proc. 11thInt,. Conf on Solid-State and Integrated Circuit Technology (ICSICT), 978 (2012).
8) K. Mistry et al., Techn. Dig. IEDM, 274 (2007).
9) C. Claeys et al., Proc. SBMicro 2013, DOI 10.1109/SBMicro.2013.66761851.
10) A. Vandooren et al., Nanoelectronics Workshop, Kyoto, Japan, 21 (2009).
11) J. Mitard et al., Jpn. J. Appl. Phys., 50, 04DC17 (2011).
12) L. Witters et al., Techn. Dig. IEDM, 534 (2013).
13) R. Rooyackers et al., Techn. Dig. IEDM, 92 (2013).
14) N. Waldron , IEEE Electron Dev. Lett., vol. 35, no. 2, 1097 (2014).