(Invited) Advanced Semiconductor Devices for Future CMOS Technologies

Tuesday, 26 May 2015: 14:00
Williford Room B (Hilton Chicago)
C. Claeys (imec, KU Leuven), D. Chiappe (imec), N. Collaert, J. Mitard (Imec), J. Radu, R. Rooyackers (imec), E. Simoen, A. Vandooren, A. Veloso (Imec), N. Waldron, L. Witters (imec), and A. Thean (Imec)
The future of Moore’s law is not only driven by silicon estate reduction, performance enhancement and cost issues, but also requires a tight control to minimize the overall power consumption.  During the last decade the device scaling has been achieved by optimization of process modules, introduction of new materials and modified device concepts. For the front-end part of standard CMOS this leads to the implementation of stress engineering, ultra-shallow junctions, gate-stacks (high-k materials, cap layers, metal gates) with EOT’s below 1 nm, optimization of process sequences (e.g. gate-first versus replacement gate or gate-last),  raised source/drain for resistance control, etc. Higher drive currents and better electrostatic control have triggered the exploration of the third dimension by going over to Multi-gate devices (MuGFETs). Parallel to the  development of CMOS on bulk silicon substrates, the use of SOI substrates received extensive attention due to the reduced process complexity in addition to enhanced electrical performance. For scaled-down technologies, fully depleted technologies with ultra-thin body and buried oxide (UTBB SOI) have demonstrated their strong potential down to the 14 nm mode (1). At those dimension there exists a strong competition between planar UTBB SOI and bulk FinFETs.

Beside changing the gate concept such as in FinFETs, devices with an operation mechanism different from thermionic emission are explored. Tunnel Field Effect Transistors (TFETs) are based on band-to-band-tunneling and allow to achieve subthreshold swings below 60 mV/dec, thereby reducing the power consumption (2). Both horizontal and vertical TFET approaches are emerging as post-CMOS alternatives with a strong potential for future technologies. Further scaling leads to gate-all-around (GAA) and nanowire devices.

    The quest for higher drive currents triggers beside stress engineering the use of mobility boosters associated with high mobility materials like Ge and III-V. The strong progress made in epitaxial growth techniques resulted in the fabrication of Ge (optimal for p-channel performance), III-V (optimal for n-channel devices) or hybrid Ge/III-V devices on a Si substrate (3). Very good performance has been demonstrated at device level. These high mobility materials are also implemented in TFET and nanowire structures.

Near the end of the roadmap the research efforts are focused towards carbon-based materials like carbon nanotubes (4) and graphene (5), spintronics (6), magnetic tunnel junctions and the use of 2D materials such as transition metal dichalcogenides (MX2) like MoS2 and NbSe2(7). For several of these approaches device feasibility has already been demonstrated.

This paper analyzes the status and the challenges of several of these advanced CMOS technologies (some of them are illustrated in Fig. 1) and outlines potential limitations for future scaling in view of important electrical parameters such as variability, noise performance and reliability. A technology benchmarking will be given.

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