(Invited) Ultralow-Voltage Design and Technology of Silicon-on Thin-Buried-Oxide (SOTB) CMOS for High Energy Efficient Electronics in IoT Era

Highly energy efficient CMOS circuits are required in theinternet-of-things (IoT) era since a great number of smallelectronic apparatuses process and communicate data. Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy (Emin) point (MEP) is effective, most of the scaled circuits operate with far higher energy than Emin. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control.[1,2] These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage.

The MEP operation is generally very slow, e.g. less than 1MHz. The variable Vth approach with adaptive back-bias control can mitigate the situation of decreasing energy as low as possible down to MEP while satisfying the required frequency. Another obstacle is the variability of transistors, which degrades operation margin especially at low Vdd. To solve these problems, we are developing silicon on thin buried oxide (SOTB) [3-4]. In this paper, we demonstrate SOTB’s small variability, back-bias control, and ULV circuit operation.

SOTB Device Results

A cross-section of the SOTB/bulk hybrid CMOS and a TEMphoto are shown in Figs. 1 and 2. The back-bias voltages, Vbn and Vbp, are applied to the well regions below BOX. The local interconnect by the silicide at the well contact region contributes to improving the back-bias voltage stability. Details of the SOTB process and electrical characteristics are described in [3].

Very small Vth and Ion variability was demonstrated [3] for one million transistors  The Pelgrom coefficient was ~1.3 mVμm, the smallest level taking the gate-oxidethickness (Tinv = 2.4 nm) into account. With this improvement, we confirmed 6-T SRAM operation (2 Mbit) at less than 0.4 V (Fig.3 (a)) with a 5.5-ps access time and demonstrated that the minimum operating voltage can be controlled at <0.4 V across whole 300mmF wafer (Fig.3 (b)). The back bias control successfully reduced the standby leakage of SRAM to 0.4pA/cell, which meet the requirement of IoT application (Fig.4). Furthermore, we demonstrated the compensation of temperature change or global variability by back bias control [3-4], resulting further improvement of operation margin at low Vdd.

SOTB Circuit Design and ULV Operation

We developed a standard cell library for the SOTB technology. The SOTB design flow is basically the same as that for the bulk technology. Using our SOTB flow, various logic circuits were designed and ULP operations were confirmed, such as an accelerator [5] and flex-power FPGA with back biasing [6]. We designed a micro-controller chip dedicated to the sensor-node application [7]. This chip operated at Vdd = 0.35 V and consumed only E = 13.4 pJ. The sleep current was only 0.14 μA. We demonstrated sensor-node operation. The CPU was operated with a single PV cell at <0.4 V. Temperature and acceleration were monitored, and only in an emergency (health problems), an alert was sent via Bluetooth low energy (BLE) to a tablet.

Acknowledgment

This work was performed as “Ultra-Low Voltage Device Project" funded and supported by METI and NEDO.

References

[1] R. Tsuchiya et al., IEDM, p. 631 (2004). [2] Y. Morita et al., VLSI Tech., p. 166, (2008). [3] Y. Yamamoto et al., VLSI Tech., p.212 (2013).  [4] H. Makiyama et al., IEDM, p.812 (2013). [5] H. Su et al., IEICE, 113, RECONF 2013-52, 71.[6] H. Koike et al., S3S Conf., 5a.5 (2013). [7] K. Ishibashi et al.,COOL Chips XVII (April 2014).