(Invited) Si Nanowire Tunnel FETs for Energy Efficient Nanoelectronics
In this paper, we will present Si nanowire TFETs. Emphasis will be placed on strained silicon n- and p-type nanowire TFETs, TFET inverters and NAND logic. We developed a simple process using ion implantation into silicide and dopant segregation (DS) to make steep tunneling junctions. TFETs with a minimum inverse subthreshold slope of 30mV/dec have been realized with trigate configuration, as shown in Fig.1. Gate all around (GAA) TFETs with nanowire diameter down to 10nm were also fabricated (Fig.2). High on-currents of ~64µA/µm at VDS=VOV=-1.0V were achieved for p-TFETs . We could show that scaled NW devices with multi-gates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path.
Inverters with complementary TFETs (C-TFET) are also presented in this paper. The C-TFET inverters show a sharp transition at a very low Vdd=0.2V (Fig.3). The experimental results of GAA p-TFET inverters and NAND demonstrate a potential of TFET for low power applications with Vdd<0.2V (Fig.4).
Finally TFETs for analog applications and perspectives of Si-Ge-Sn TFETs will be presented.
Acknowledgement: The research leading to these results has received funding from the European Community’s Seventh Framework Programme under grant agreement No. 619509 (project E2SWITCH) and the German BMBF project “UltraLowPower” (16ES0060K).
 L. Knoll, Q.T. Zhao, A. Nichau, S. Trellenkamp, S. Richter, A. Schäfer, D. Esseni, L. Selmi, K. K. Bourdelle, and S. Mantl, Electron Device Letters, IEEE, vol. 34, no. 6, pp. 813–815, 2013.