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Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

_{T}) control, better reliability, better power efficiency at high frequency operation, higher compatibility with existing CMOS technology (1).

In PDSOI a technique has been proposed to further improve some digital and analog parameter, called dynamic threshold (DT) MOS mode, where the front gate (V_{GF}) is connected to the body. During the V_{GF} sweep, the body bias is also increased, which dynamically reduces the V_{T}. (2)

In UTBB FDSOI devices, this concept has been applied in 3 operation modes: the simple DT (V_{GB }= V_{GF}) (3,4), the enhanced DT (V_{GB }= kV_{GF}) (3,4) and the inverse DT (V_{GF }= kV_{GB}) (4). In this case, the V_{GF} is tied to the V_{GB}, instead of the body and the V_{T} is decreased when V_{GB} increases. (3,4).

Figure 1 schematically shows a DT-UTBB SOI structure. The device that was used in this work was fabricated in imec, Belgium. The SOI wafer has a nominal value for silicon film thickness (t_{Si}) of 20 nm and buried oxide thickness (t_{oxb}) of 10 nm. The front oxide thickness (t_{oxf}) is 5 nm. The gate material is TiN. The dimensions of the device are channel length (L) of 105 nm and the channel width of 920 nm. A p-type ground plane (GP) implantation was done which is considered as a back gate. More process information can be found in (5).

The goal of this work is to determine the V_{T} of DT UTBB SOI transistors using a simple analytical model proposed by Martino et al (6), with quantum confinement effect (7,8). The equations [1], [2] and [3] were used to determine the value of V_{T} and the equations [4], [5] and [6] represent the variation of t_{Si} and t_{oxf} due to the quantum confinement effect. In the analytical model, the GP concentration was set to 10^{18}cm^{-3} and the metal work function at 4.62 V (TiN).

By the V_{T} x V_{GB} curve calculated from the analytical model, it is possible to determine the value of V_{T} of the UTBB operating in: DT, eDT and inverse-eDT modes.

In figure 2 the straight line represents the analytical model V_{T} as a function of V_{GB}, and the dashed lines are related to the following conditions: V_{GB} = V_{GF}, V_{GB} = kV_{GF} and V_{GF} = kV_{GB}, for k = 2. These curves represent the three operation modes of DT: simple DT, enhanced DT and inverse eDT mode respectively. The intersection points between the dashed and the straight lines represent the extraction point of V_{T} of a device in DT, eDT and inverse eDT mode, respectively. For DT and eDT modes the V_{T} of DT UTBB SOI is the value of V_{T} of intersection point (Y-axis). In case of inverse eDT the V_{T} is represent by the value of V_{GB} of the intersection (X-axis). The same analysis was done for different values of k.

The value of V_{T} obtained from figure 2 was compared with experimental data in figure 3 and a good agreement was observed. In figure 3, for k=0 the operation mode of the transistor is the conventional mode, where V_{GB} = 0V. This method of extraction of the threshold voltage in DT UTBB devices is simple and effective.

(1) B.-Y. Nguyen et al., Advanced Substrate News (2014).

(2) J.P. Colinge, IEEE Trans. Electron Devices, 44, 845 (1987).

(3) V. Kilchytska et al., Solid State Electronics, 84, 28-37 (2013).

(4) K.R.A. Sasaki et al., Proceedings of the IX ICCDCS Conference, 57 (2014).

(5) N. Collaert et al., Proceedings of IEEE International SOI Conference, 1 (2009).

(6) J.A. Martino et al., Electron Letters, 26, 1462-1464 (1990).

(7) S. Burignat et al., Solid-State Electronics, 54, 213-219 (2010).