Threshold Voltage Modeling for Dynamic Threshold UTBB SOI in Different Operation Modes

Wednesday, 27 May 2015: 15:00
Williford Room B (Hilton Chicago)
V. T. Itocazu, K. R. A. Sasaki, M. B. Manini (University of Sao Paulo), V. Sonnenberg (FATEC Sao Paulo e FATEC Osasco, University of Sao Paulo), J. A. Martino (University of Sao Paulo), E. Simoen (imec), and C. Claeys (KU Leuven, imec)
UTBB FDSOI (Ultrathin-Body-and-Buried-Oxide Fully-Depleted-SOI) devices have been studied for the 14nm and 10nm technology nodes, thanks to reduced SCEs, better threshold voltage (VT) control, better reliability, better power efficiency at high frequency operation, higher compatibility with existing CMOS technology (1).

In PDSOI a technique has been proposed to further improve some digital and analog parameter, called dynamic threshold (DT) MOS mode, where the front gate (VGF) is connected to the body. During the VGF sweep, the body bias is also increased, which dynamically reduces the VT. (2)

In UTBB FDSOI devices, this concept has been applied in 3 operation modes: the simple DT   (VGB = VGF) (3,4), the enhanced DT (VGB = kVGF) (3,4) and the inverse DT (VGF = kVGB) (4). In this case, the VGF is tied to the VGB, instead of the body and the VT is decreased when VGB increases. (3,4).

Figure 1 schematically shows a DT-UTBB SOI structure. The device that was used in this work was fabricated in imec, Belgium. The SOI wafer has a nominal value for silicon film thickness (tSi) of 20 nm and buried oxide thickness (toxb) of 10 nm. The front oxide thickness (toxf) is 5 nm. The gate material is TiN. The dimensions of the device are channel length (L) of 105 nm and the channel width of 920 nm.  A p-type ground plane (GP) implantation was done which is considered as a back gate. More process information can be found in (5).

The goal of this work is to determine the VT of DT UTBB SOI transistors using a simple analytical model proposed by Martino et al (6), with quantum confinement effect (7,8). The equations [1], [2] and [3] were used to determine the value of VT and the equations [4], [5] and [6] represent the variation of tSi and toxf due to the quantum confinement effect. In the analytical model, the GP concentration was set to 1018cm-3 and the metal work function at 4.62 V (TiN).

By the VT x VGB curve calculated from the analytical model, it is possible to determine the value of VT of the UTBB operating in: DT, eDT and inverse-eDT modes.

In figure 2 the straight line represents the analytical model VT as a function of VGB, and the dashed lines are related to the following conditions: VGB = VGF, VGB = kVGF and VGF = kVGB, for k = 2. These curves represent the three operation modes of DT: simple DT, enhanced DT and inverse eDT mode respectively. The intersection points between the dashed and the straight lines represent the extraction point of VT of a device in DT, eDT and inverse eDT mode, respectively. For DT and eDT modes the VT of DT UTBB SOI is the value of VT of intersection point (Y-axis). In case of inverse eDT the VT is represent by the value of VGB of the intersection (X-axis). The same analysis was done for different values of k.

The value of VT obtained from figure 2 was compared with experimental data in figure 3 and a good agreement was observed. In figure 3, for k=0 the operation mode of the transistor is the conventional mode, where VGB = 0V. This method of extraction of the threshold voltage in DT UTBB devices is simple and effective.

(1)          B.-Y. Nguyen et al., Advanced Substrate News (2014).

(2)          J.P. Colinge, IEEE Trans. Electron Devices, 44, 845 (1987).

(3)          V. Kilchytska et al., Solid State Electronics, 84, 28-37 (2013).

(4)          K.R.A. Sasaki et al., Proceedings of the IX ICCDCS Conference, 57 (2014).

(5)          N. Collaert et al., Proceedings of IEEE International SOI Conference, 1 (2009).

(6)          J.A. Martino et al.,  Electron Letters, 26, 1462-1464 (1990).

(7)          S. Burignat et al., Solid-State Electronics, 54, 213-219 (2010).