The Impact of the Ge Concentration in the Source for Vertical Tunnel-FETs
All analyzed vertical nanowire TFETs were fabricated at imec/Belgium with the following characteristics: gate stack composed by a dielectric of 3nm HfO2 on top of 1nm interfacial SiO2 covered by a TiN metal and amorphous silicon layer. Four different source compositions are studied: Si(100%), Si0.73Ge0.27, Si0.56Ge0.44and Ge(100%). More process details can be found in (2,3). Each device used in this work is composed of 100 nanowires in parallel. A schematical view of one nanowire can be seen in figure 1.
The impact of the source composition on the TFET behavior can be evaluated in figure 2. By increasing the germanium amount of the source, the bandgap decreases which results in an increased BTBT generation rate and a higher on-state current (ION) without degrading IOFF, resulting in a better subthreshold swing.
Figure 3 shows the influence of %Ge on the NW-TFET transconductance (gm) and output conductance (gD). As can be observed in figure 3, when %Ge increases, gm also increases thanks to the higher tunneling current at the source side. However, the gD becomes worse due to the higher influence of the drain electric field on the drain current for devices dominated by a higher BTBT current (4).
The intrinsic voltage gain (AV=gm/gD) presents an optimum point around 27% of Ge due to a competition between the gm and gD behavior. From 0 to 27% of Ge, the gm is the predominant parameter thanks to the increase of BTBT current. For higher %Ge, the drain electric field is the dominant gD degradation factor, since the devices are operating at a higher level of the BTBT component (4).
In order to better understand the effect of the Ge amount at the TFET source, the low-frequency noise spectra of Si1−xGex devices were analyzed. The lowest current noise PSD was obtained for the Si source sample (about one order of magnitude lower 1/f noise at 10 Hz). This suggests that the presence of Ge at the interface with the gate dielectric may be responsible for this observation. Similar results have already been observed for Si1−xGex channel MOSFETs, where the 1/f noise increases with Ge content, resulting in an increase of traps and defects at the interface and in the dielectric layer (5,6).
A more detailed analysis about TFETs with different Ge amount at the source terminal will be presented at the conference.
1. W. Y. Choi et al., IEEE Electron Device Lett. 28, 743 (2007).
2. R. Rooyackers et al., IEDM, 92 (2013).
3. Vandooren, A. Solid State Electronics, Vol. 83, p.50 (2013).
4. P. G. D. Agopian et al., IEEE Trans. Electron Device, DOI: 10.1109/TED.2014.2367659, (2014).
5. A. Tanabe et al.,Proc. Electrochem. Soc., 2004, pp. 483–492.