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1455
(Invited) Power Loss Reduction in Perforated-Channel HFET Switches

(Invited) Power Loss Reduction in Perforated-Channel HFET Switches

Tuesday, 26 May 2015: 14:00

Conference Room 4C (Hilton Chicago)

The key factors affecting the efficiency of power electronic systems are the conduction and switching losses in semiconductor power switches. For field-effect transistor switches, the conduction power loss is proportional to the product of the squared current,

*I*, flowing through the switch in the on-state and the switching loss is proportional to the squared maximum switch voltage,_{ON}*V*the effective device output capacitance,_{MAX, }*C*, and the switching frequency,_{OUT}*f*. Therefore, the_{SW}*R*_{ON}C_{OUT}_{ }product is an important figure of merit of a FET-type switch determining the overall power efficiency. Our proposed and implemented Perforated Channel (PC) FET design^{1}allowed us to significantly reduce*R*but not_{ON}**,***C*We now propose and demonstrate the improved PC-HFET design that allows us to reduce both_{OUT}.*R*. This design reduces the power losses and significantly improves the efficiency of power electronics systems. In the PC-HFET, the portions of the channel under the gate are removed and the remaining channel forms a dash-line of islands_{ON}and C_{OUT}*W*wide with W_{G1}_{GG}spacing between them. The channel “filling factor” in PC-HFET is*k*). Compared to conventional HFET with the same total width_{F}= W_{G1}/(W_{G1}+W_{GG}*W*, the total channel width and, hence, the device gate capacitance, of the PC-HFET is*k*times smaller. However, our analytical estimates, numerical simulations (using the 3D simulation in Synopsys Sentaurus device simulator), and experimental data all show the on-resistance of the PC-HFET can be only 10-15% higher than that of the conventional HFET of the same width. This is achieved due to a strong current spreading effect in the source-to-gate and, especially, in a larger gate-to-drain spacing. The gate capacitance of PC-HFET reduces proportionally to the_{F}*k*factor as proven by our simulations and experimental data presented in [1]. However our 3D simulations show that the_{F}*C*scaling in PC-HFET at high drain voltage is nearly the same as that for conventional HFET. To reduce this capacitance, we proposed the PC-HFET device design with the holes extending into the gate-drain spacing. Our simulations show that the hole extension allows for nearly the same_{GD}*C*reduction as the gate metal removal over the holes. We used the obtained_{GD}*R*and_{ON}*C*data to calculate the power loss in AlGaN/GaN PC-HFET and showed that the PC-HFET design filling factor_{GD}*k*= 0.25 reduces the total conversion loss in the power switch by more than a factor of 2._{F}[1] G. Simin, M. Islam, M. Gaevski, J. Deng, R. Gaska, and M. Shur, “Low RC-constant Perforated-Channel HFET”, IEEE El. Dev. Letters, V. 35, pp.449-451, 2014