(Invited) Power Loss Reduction in Perforated-Channel HFET Switches

Tuesday, 26 May 2015: 14:00
Conference Room 4C (Hilton Chicago)
M. Shur (Rensselaer Polytechnic Institute), M. Gaevski, R. Gaska (Sensor Electronic Technology, Inc.), G. Simin (University of South Carolina), H. Y. Wong, N. Braga, and R. Mickevicius (SYNOPSYS, Inc.)
The key factors affecting the efficiency of power electronic systems are the conduction and switching losses in semiconductor power switches. For field-effect transistor switches, the conduction power loss is proportional to the product of the squared current, ION, flowing through the switch in the on-state and the switching loss is proportional to the squared maximum switch voltage, VMAX, the effective device output capacitance, COUT, and the switching frequency, fSW. Therefore, the RONCOUT product is an important figure of merit of a FET-type switch determining the overall power efficiency. Our proposed and implemented Perforated Channel (PC) FET design 1 allowed us to significantly reduce RON, but not COUT. We now propose and demonstrate the improved PC-HFET design that allows us to reduce both RON and COUT. This design reduces the power losses and significantly improves the efficiency of power electronics systems. In the PC-HFET, the portions of the channel under the gate are removed and the remaining channel forms a dash-line of islands WG1 wide with WGG spacing between them. The channel “filling factor” in PC-HFET is kF = WG1/(WG1+WGG). Compared to conventional HFET with the same total width W, the total channel width and, hence, the device gate capacitance, of the PC-HFET is kF times smaller. However, our analytical estimates, numerical simulations (using the 3D simulation in Synopsys Sentaurus device simulator), and experimental data all show the on-resistance of the PC-HFET can be only 10-15% higher than that of the conventional HFET of the same width. This is achieved due to a strong current spreading effect in the source-to-gate and, especially, in a larger gate-to-drain spacing. The gate capacitance of PC-HFET reduces proportionally to the kF factor as proven by our simulations and experimental data presented in [1]. However our 3D simulations show that the CGD scaling in PC-HFET at high drain voltage is nearly the same as that for conventional HFET. To reduce this capacitance, we proposed the PC-HFET device design with the holes extending into the gate-drain spacing. Our simulations show that the hole extension allows for nearly the same CGD reduction as the gate metal removal over the holes. We used the obtained RON and CGD data to calculate the power loss in AlGaN/GaN PC-HFET and showed that the PC-HFET design filling factor kF = 0.25 reduces the total conversion loss in the power switch by more than a factor of 2.

[1] G. Simin, M. Islam, M. Gaevski, J. Deng, R. Gaska, and M. Shur, “Low RC-constant Perforated-Channel HFET”, IEEE El. Dev. Letters, V. 35, pp.449-451, 2014